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? copyright 2000 advanced micro devices, inc. all rights reserved . publication# 21915 rev: b amendment/ 0 issue date: may 2000 am186 ? cc high-performance, 80c186-compatible 16-bit embedded communications controller distinctive characteristics n e 86? family of x86 embedded processors offers improved time-to-market C software migration (backwards- and upwards- compatible) C world-class development tools, applications, and system software n serial communications peripherals C four high-level data link control (hdlc) channels C four independent time slot assigners (tsas) C physical interface for hdlc channels can be raw dce, pcm highway, or gci (iom-2) C usb peripheral controller C high-speed uart with autobaud Cuart C synchronous serial interface (ssi) C smartdma? channels (8) to support usb/hdlc n system peripherals C three programmable 16-bit timers C hardware watchdog timer C general-purpose dma (4 channels) C programmable i/o (48 pio signals) C interrupt controller (36 maskable interrupts) n memory and peripheral interface C integrated dram controller C glueless interface to ram/rom/flash memory (55-ns flash memory required for zero-wait-state operation at 50 mhz) C fourteen chip selects (8 peripherals, 6 memory) C external bus mastering support C multiplexed and nonmultiplexed address/data bus C programmable bus sizing C 8-bit boot option n available in the following package C 160-pin plastic quad flat pack (pqfp) C 25-, 40-, and 50-mhz operating frequencies C low-voltage operation, v cc = 3.3 v 0.3 v C commercial and industrial temperature rating C 5-v-tolerant i/o (3.3-v output levels) general description the am186?cc embedded communications controller is the first member in the amd comm86? product family. the AM186CC controller is a cost- effective, high-performance microcontroller solution for communications applications. this highly integrated microcontroller enables customers to save system costs and increase performance over 8-bit microcontrollers and other 16-bit microcontrollers. the AM186CC communications controller offers the advantages of the x86 development environments widely available native development tools, applications, and system software. additionally, the controller uses the industry-standard 186 instruction set that is part of the amd e86? family, which continually offers instruction-set-compatible upgrades. built into the AM186CC controller is a wide range of communications features required in many communications applications, including high-level data link control (hdlc) and the universal serial bus (usb). amd offers complete solutions with the AM186CC controller. a customer development platform board is available. reference designs under development include a low-end router with integrated services digital network (isdn), ethernet, usb, plain old telephone service (pots), and an isdn terminal adapter featuring usb. amd and its fusione86 sm partners offer boards, schematics, drivers, protocol stacks, and routing software for these reference designs to enable fast time to market.
2 am186?cc communications controller data sheet ordering information C25 = 25 mhz C40 = 40 mhz C50 = 50 mhz temperature range speed option device number/description lead forming \w=trimmed and formed valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations package type k=160-pin plastic quad flat pack (pqfp) AM186CC high-performance 80c186-compatible 16-bit embedded communications controller C50 k c \w valid combinations AM186CC C25 AM186CCC40 AM186CCC50 kc\w AM186CCC25 AM186CCC40 ki\w AM186CC c= AM186CC commercial (t c =0 ? c to +100 ? c) i = AM186CC industrial (t a =C40 ? c to +85 ? c) where: t c = case temperature where: t a = ambient temperature
am186?cc communications controller data sheet 3 table of contents distinctive characteristics ................................................................................................... ......... 1 general description ........................................................................................................... .......... 1 ordering information .......................................................................................................... .......... 2 logic diagram by interface .................................................................................................... ...... 6 logic diagram by default pin function ....................................................................................... 7 pin connection diagram160-pin pqfp package .................................................................... 8 pin and signal tables ......................................................................................................... ......... 9 signal descriptions ........................................................................................................... .... 13 architectural overview ........................................................................................................ ....... 28 detailed description .......................................................................................................... .... 28 am186 embedded cpu ........................................................................................................ 29 memory organization ........................................................................................................... .29 i/o space ..................................................................................................................... ......... 29 serial communications support ............................................................................................ 30 universal serial bus ......................................................................................................... 3 0 four hdlc channels and four tsas.............................................................................. 31 general circuit interface .................................................................................................. 31 eight smartdma? channels........................................................................................... 31 two asynchronous serial ports ....................................................................................... 31 synchronous serial port................................................................................................... 32 system peripherals ............................................................................................................ ... 32 interrupt controller ........................................................................................................... 32 four general-purpose dma channels ............................................................................ 32 48 programmable i/o signals .......................................................................................... 32 three programmable timers ........................................................................................... 32 hardware watchdog timer .............................................................................................. 33 memory and peripheral interface .......................................................................................... 33 system interfaces............................................................................................................. 33 dram support ................................................................................................................. 3 4 chip selects ................................................................................................................... .. 34 clock control ................................................................................................................. ........ 35 in-circuit emulator support ................................................................................................... 37 applications .................................................................................................................. ............. 37 clock generation and control .................................................................................................. .40 features ...................................................................................................................... .......... 40 system clock .................................................................................................................. ...... 40 usb clock ..................................................................................................................... ........ 40 clock sharing by system and usb ....................................................................................... 41 crystal-driven clock source ................................................................................................. 42 external clock source ......................................................................................................... .. 43 static operation .............................................................................................................. ...... 43 pll bypass mode ............................................................................................................... .. 43 uart baud clock ............................................................................................................... .. 43 power supply operation ........................................................................................................ .... 44 power supply connections ................................................................................................... 44 input/output circuitry ........................................................................................................ .... 44 pio supply current limit ...................................................................................................... 44 absolute maximum ratings ...................................................................................................... .45 operating ranges .............................................................................................................. ........ 45 driver characteristicsuniversal serial bus ............................................................................ 45 dc characteristics over commercial and industrial operating ranges .................................... 46 capacitance ................................................................................................................... ............ 46
4 am186?cc communications controller data sheet maximum load derating ......................................................................................................... ... 47 power supply current .......................................................................................................... ...... 47 thermal characteristics ....................................................................................................... ...... 48 pqfp package .................................................................................................................. ... 48 commercial and industrial switching characteristics and waveforms ...................................... 49 switching characteristics over commercial and industrial operating ranges ......................................58 appendix apin tables .......................................................................................................... ..a-1 pin list table column definitions ......................................................................................a-11 appendix bphysical dimensions: pqr160, plastic quad flat pack (pqfp) ........................b-1 appendix ccustomer support ...............................................................................................c-1 related amd productse86? family devices ..................................................................c-1 related documents ............................................................................................................. .c-2 AM186CC/ch/cu microcontroller customer development platform ..................................c-2 third-party development support products .................................................................................c-2 customer service .............................................................................................................. ...c-2 hotline and world wide web support............................................................................. c-2 corporate applications hotline........................................................................................ c-2 world wide web home page ......................................................................................... c-3 documentation and literature ......................................................................................... c-3 literature ordering .......................................................................................................... c -3 index .......................................................................................................................... ......... index-1 list of figures figure 1. AM186CC controller block diagram ..................................................................... 28 figure 2. two-component address example ...................................................................... 30 figure 3. AM186CC controller address bus default operation ...................................... 35 figure 4. AM186CC controlleraddress bus disable in effect .......................................... 36 figure 5. isdn terminal adapter system application ......................................................... 38 figure 6. isdn to ethernet low-end router system application ........................................ 38 figure 7. 32-channel linecard system application ............................................................. 39 figure 8. system and usb clock generation ...................................................................... 41 figure 9. suggested system clock frequencies, clock modes, and crystal frequencies . 42 figure 10. external interface to support clocksfundamental mode crystal ...................... 42 figure 11. external interface to support clocksexternal clock source ............................. 43 figure 12. uart and high-speed uart clocks ................................................................... 43 figure 13. typical i cc versus frequency ................................................................................ 47 figure 14. thermal resistance( ? c/watt) ............................................................................... 48 figure 15. thermal characteristics equations ....................................................................... 48 figure 16. key to switching waveforms ................................................................................ 49 figure 17. read cycle waveforms ........................................................................................ 60 figure 18. write cycle waveforms ......................................................................................... 63 figure 19. software halt cycle waveforms ........................................................................... 64 figure 20. peripheral timing waveforms ............................................................................... 65 figure 21. reset waveforms .................................................................................................. 66 figure 22. signals related to reset (system pll in 1x or 2x mode) .................................... 67 figure 23. signals related to reset (system pll in 4x mode) ............................................. 67 figure 24. synchronous ready waveforms ........................................................................... 68 figure 25. asynchronous ready waveforms ......................................................................... 69 figure 26. entering bus hold waveforms .............................................................................. 70 figure 27. exiting bus hold waveforms ................................................................................. 70 figure 28. system clock timing waveformsactive mode (pll 1x mode) ......................... 72 figure 29. usb clock timing waveforms .............................................................................. 72 figure 30. gci bus waveforms ............................................................................................. 73
am186?cc communications controller data sheet 5 figure 31. pcm highway waveforms (timing slave) ............................................................ 75 figure 32. pcm highway waveforms (timing master) .......................................................... 76 figure 33. dce transmit waveforms .................................................................................... 77 figure 34. dce receive waveforms ..................................................................................... 77 figure 35. usb data signal rise and fall times .................................................................. 78 figure 36. usb receiver jitter tolerance .............................................................................. 78 figure 37. synchronous serial interface waveforms ............................................................. 79 figure 38. dram read cycle without wait-states waveform ............................................... 80 figure 39. dram read cycle with wait-states waveform .................................................... 81 figure 40. dram write cycle without wait-states waveform ............................................... 81 figure 41. dram write cycle with wait-states waveform .................................................... 82 figure 42. dram refresh cycle waveform ........................................................................... 82 list of tables table 1. pqfp pin assignmentssorted by pin number .................................................. 10 table 2. pqfp pin assignmentssorted by signal name ................................................ 11 table 3. signal description table definitions ...................................................................... 13 table 4. signal descriptions ............................................................................................... 14 table 5. segment register selection rules ....................................................................... 30 table 6. crystal parameters ................................................................................................ 42 table 7. typical power consumption calculation................................................................ 47 table 8. thermal characteristics ( ? c/watt) ........................................................................ 48 table 9. alphabetical key to switching parameter symbols .............................................. 50 table 10. numerical key to switching parameter symbols .................................................. 54 table 11. read cycle timing ................................................................................................ 58 table 12. write cycle timing ................................................................................................ 61 table 13. software halt cycle timing ................................................................................... 64 table 14. peripheral timing .................................................................................................. 65 table 15. reset timing ......................................................................................................... 66 table 16. external ready cycle timing ................................................................................ 68 table 17. bus hold timing .................................................................................................... 69 table 18. system clocks timing ........................................................................................... 71 table 19. usb clocks timing ............................................................................................... 72 table 20. gci bus timing ..................................................................................................... 73 table 21. pcm highway timing (timing slave) ................................................................... 74 table 22. pcm highway timing (timing master) ................................................................. 76 table 23. dce interface timing ............................................................................................ 77 table 24. usb timing ........................................................................................................... 78 table 25. ssi timing ........................................................................................................... .. 79 table 26. dram timing ........................................................................................................ 80 table 27. power-on reset (por) pin defaults ...................................................................a-2 table 28. multiplexed signal trade-offs ...............................................................................a-5 table 29. pios sorted by pio number ................................................................................a-8 table 30. pios sorted by signal name ...............................................................................a-9 table 31. reset configuration pins (pinstraps) .................................................................a-10 table 32. cpu pll modes .................................................................................................a-10 table 33. usb pll modes..................................................................................................a-10 table 34. pin list table definitions.....................................................................................a-11 table 35. pin list summary ...............................................................................................a-12
6 am186?cc communications controller data sheet logic diagram by interface 1 clkout int8Cint0 interrupts reset/ res nmi clocks resout x1 lcs chip selects x2 mcs3 Cmcs0 pcs7 Cpcs0 address and address/data buses a19Ca0 ucs ad15Cad0 cas0 dram control bus status and control ale cas1 ardy ras0 bhe ras1 bsize8 den dce_rxd_a, b, c, d dce interface (hdlc aCd) 1 notes: 1. because of multiplexing, not all interfaces are available at once. refer to table 28, multiplexed signal trade-offs, on page a-5. ds dce_txd_a, b, c, d drq1Cdrq0 dce_rclk_a, b, c, d dt/r dce_tclk_a, b, c, d hlda dce_cts_a , b , c , d hold dce_rtr_a , b , c , d rd s2 Cs0 pcm_rxd_a, b, c, d pcm interface (hdlc aCd) 1 s6 pcm_txd_a, b, c, d srdy pcm_clk_a, b, c, d whb pcm_fsc_a, b, c, d wlb pcm_tsc_a , b , c , d wr gci_dd_a gci interface (hdlc a) 1 programmable timers pwd gci_du_a tmrin1Ctmrin0 gci_dcl_a tmrout1Ctmrout0 gci_fsc_a debug qs1Cqs0 usbd+ universal serial bus (usb) usbdC synchronous serial interface sden usbsci sclk usbsof sdata usbx1 usbx2 asynchronous serial interface (uart) rxd_u txd_u udmns usb external transceiver interface cts_u udpls rtr_u utxdmns utxdpls high-speed uart rxd_hu uxvoe txd_hu uxvrcv cts_hu rtr_hu {aden } configuration pinstraps {clksel1} uart clock uclk {clksel2} {once } programmable i/o (pio) pio47Cpio0 {ucsx8 } {usbsel1} {usbsel2} {usbxcvr } 9 / 4 / 8 / 20 16 4 / 4 / 2 / 4 / 4 / 4 / 4 / 3 / 4 / 4 / 4 / 4 / 4 / 2 / 2 / 2 /
am186?cc communications controller data sheet 7 logic diagram by default pin function 1 notes: 1. pin names in bold indicate the default pin function. brackets, [ ], indicate alternate, multiplexed functions. braces, { }, indicate pinstrap pi ns. clkout reset/ res clocks resout dce_rxd_a [gci_dd_a] [pcm_rxd_a] hdlc a (dce) x1 dce_txd_a [gci_du_a] [pcm_txd_a] x2 dce_rclk_a [gci_dcl_a] [pcm_clk_a] dce_tclk_a [gci_fsc_a] [pcm_fsc_a] address and address/data buses a19Ca0 ad15Cad0 pio0 [tmrin1] bus status and control ale [pio33] pio1 [tmrout1] programmable i/o (pio) ardy [pio8] pio2 [pcs5] bhe [pio34] {aden } pio3 [pcs4 ] {clksel2} bsize8 pio4 [mcs0 ] {ucsx8 } den [ds ] [pio30] pio5 [mcs3 ] [ras1 ] drq1 pio6 [int8] [pwd] dt/r [pio29] pio7 [int7] hlda {clksel1} pio8 [ardy] hold rd pio9 [drq0] s0 {usbxcvr } pio10 [sden] s1 pio11 [sclk] s2 pio12 [sdata] s6 srdy [pio35] pio16 [rxd_hu] whb pio17 [dce_cts_a ] [pcm_tsc_a ] wlb pio18 [dce_rtr_a ] wr [pio15] pio19 [int6] pio20 [txd_u] [dce_txd_d] [pcm_txd_d] debug qs1Cqs0 pio21 [uclk] [usbsof] [usbsci] pio22 [dce_rclk_c] [pcm_clk_c] high-speed uart txd_hu pio23 [dce_tclk_c] [pcm_fsc_c] pio24 [cts_u ] [dce_tclk_d] [pcm_fsc_d] chip selects lcs [ras0 ] pio25 [rtr_u ] [dce_rclk_d] [pcm_clk_d] mcs1 [cas1 ] pio26 [rxd_u] [dce_rxd_d] [pcm_rxd_d] mcs2 [cas0 ] pio27 [tmrin0] pcs0 [pio13] {usbsel1} pio28 [tmrout0] pcs1 [pio14] {usbsel2} pcs2 pio31 [pcs7 ] pcs3 pio32 [pcs6 ] ucs {once } pio36 [dce_rxd_b] [pcm_rxd_b] universal serial bus (usb) usbd+ [udpls] pio37 [dce_txd_b] [pcm_txd_b] usbdC [udmns] pio38 [dce_cts_b ] [pcm_tsc_b ] usbx1 pio39 [dce_rtr_b ] usbx2 pio40 [dce_rclk_b] [pcm_clk_b] pio41 [dce_tclk_b] [pcm_fsc_b] interrupts int5Cint0 pio42 [dce_rxd_c] [pcm_rxd_c] nmi pio43 [dce_txd_c] [pcm_txd_c] pio44 [dce_cts_c ] [pcm_tsc_c ] pio45 [dce_rtr_c ] pio46 [cts_hu ] [dce_cts_d ] [pcm_tsc_d ] pio47 [rtr_hu ] [dce_rtr_d ] no connection rsvd_104 [uxvrcv] rsvd_103 [uxvoe ] rsvd_102 [utxdmns] rsvd_101 [utxdpls] 20 16 6 /
8 am186?cc communications controller data sheet pin connection diagram160-pin pqfp package v cc txd_u/dce_txd_d/pcm_txd_d rxd_u/dce_rxd_d/pcm_rxd_d cts_u /dce_tclk_d/pcm_fsc_d rtr_u /dce_rclk_d/pcm_clk_d v ss dce_txd_c/pcm_txd_c dce_rxd_c/pcm_rxd_c dce_cts_c /pcm_tsc_c dce_rtr_c dce_rclk_c/pcm_clk_c dce_tclk_c/pcm_fsc_c v cc int8/pwd int7 int6 tmrin1 tmrout1 tmrin0 tmrout0 v ss dce_txd_b/pcm_txd_b dce_rxd_b/pcm_rxd_b dce_cts_b /pcm_tsc_b dce_rtr_b dce_rclk_b/pcm_clk_b dce_tclkb/pcm_fsc_b v cc ucs {once } lcs /ras0 v ss mcs3 /ras1 mcs2 /cas0 mcs1 /cas1 mcs0 {ucsx8 } v cc drq0 dce_cts_a /pcm_tsc_a dce_rtr_a v ss 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1v ss v cc 120 2 sden dce_txd_a/gci_du_a/pcm_txd_a 119 3 sclk dce_rxd_a/gci_dd_a/pcm_rxd_a 118 4 sdata dce_rclk_a/gci_dcl_a/pcm_clk_a 117 5pcs0 {usbsel1} dce_tclk_a/gci_fsc_a/pcm_fsc_a 116 6pcs1 {usbsel2} nmi 115 7pcs2 res 114 8pcs3 int5 113 9pcs4 {clksel2} int4 112 10 pcs5 int3 111 11 pcs6 int2 110 12 v cc int1 109 13 pcs7 v ss 108 14 ardy int0 107 15 srdy v cc 106 16 wr drq1 105 17 dt/r rsvd_104/uxvrcv 104 18 den /ds rsvd_103/uxvoe 103 19 ale rsvd_102/utxdmns 102 20 bhe {aden } rsvd_101/utxdpls 101 21 v ss v ss 100 22 uclk/usbsof/usbsci hold 99 23 rtr_hu /dce_rtr_d hlda {clksel1} 98 24 cts_hu /dce_cts_d /pcm_tsc_d rd 97 25 rxd_hu wlb 96 26 txd_hu whb 95 27 v cc bsize8 94 28 ad0 ad15 93 29 ad8 ad7 92 30 a0 v cc 91 31 a1 a19 90 32 a2 a18 89 33 v ss a17 88 34 ad1 ad14 87 35 ad9 ad6 86 36 a3 a16 85 37 a4 a15 84 38 ad2 v ss 83 39 ad10 v ss _usb 82 40 v cc usbd+/udpls 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 v ss a5 a6 a7 a8 ad3 ad11 v cc a9 a10 ad4 ad12 v ss s6 s2 s1 s0 {usbxcvr } resout v cc clkout v ss qs0 qs1 a11 a12 ad5 ad13 vcc a13 a14 v ss v ss _a x1 x2 usbx1 usbx2 v cc _a v cc v cc _usb usbd-/udmns
am186?cc communications controller data sheet 9 pin and signal tables table 1 on page 10 and table 2 on page 11 show the pins sorted by pin number and signal name, respectively. table 4 on page 14 contains the signal descriptions (grouped alphabetically and by function). the table includes columns listing the multiplexed functions and i/o type. table 3 on page 13 shows terms used in ta b l e 4 . refer to appendix a, pin tables, on page a-1 for an additional group of tables with the following information: n power-on reset (por) pin defaults including pin numbers and multiplexed functionstable 27 on page a-2. n multiplexed signal trade-offstable 28 on page a-5. n programmable i/o (pio) pins ordered by pio pin number and multiplexed signal name, respectively, including columns listing multiplexed functions and pin configurations following system resettable 29 on page a-8 and table 30 on page a-9. n pinstraps and pinstrap optionstable 31 on page a-10. n pin and signal summary showing signal name and alternate function, pin number, i/o type, load values, por default function, reset state, por default operation, hold state, and voltagetable 35 on page a-12. in all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). the line over a pin name indicates an active low. the word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it.
10 am186?cc communications controller data sheet table 1. pqfp pin assignmentssorted by pin number 1 pin no. nameleft side pin no. namebottom side pin no. nameright side pin no. nametop side 1v ss 41 v ss 81 usbd+/udpls 121 v ss 2sden 42a5 82v ss _usb 122 dce_rtr_a 3 sclk 43 a6 83 v ss 123 dce_cts_a / pcm_tsc_a 4 sdata 44 a7 84 a15 124 drq0 5pcs0 {usbsel1} 45 a8 85 a16 125 v cc 6pcs1 {usbsel2} 46 ad3 86 ad6 126 mcs0 {ucsx8 } 7pcs2 47 ad11 87 ad14 127 mcs1 /cas1 8pcs3 48 v cc 88 a17 128 mcs2 /cas0 9pcs4 {clksel2} 49 a9 89 a18 129 mcs3 /ras1 10 pcs5 50 a10 90 a19 130 v ss 11 pcs6 51 ad4 91 v cc 131 lcs /ras0 12 v cc 52 ad12 92 ad7 132 ucs {once } 13 pcs7 53 v ss 93 ad15 133 v cc 14 ardy 54 s6 94 bsize8 134 dce_tclk_b/ pcm_fsc_b 15 srdy 55 s2 95 whb 135 dce_rclk_b/ pcm_clk_b 16 wr 56 s1 96 wlb 136 dce_rtr_b 17 dt/r 57 s0 {usbxcvr }97rd 137 dce_cts_b / pcm_tsc_b 18 den /ds 58 resout 98 hlda {clksel1} 138 dce_rxd_b/ pcm_rxd_b 19 ale 59 v cc 99 hold 139 dce_txd_b/ pcm_txd_b 20 bhe {aden } 60 clkout 100 v ss 140 v ss 21 v ss 61 v ss 101 rsvd_101/utxdpls 141 tmrout0 22 uclk/usbsof/usbsci 62 qs0 102 rsv d_102/utxdmns 142 tmrin0 23 rtr_hu /dce_rtr_d 63 qs1 103 rsvd_103/uxvoe 143 tmrout1 24 cts_hu /dce_cts_d / pcm_tsc_d 64 a11 104 rsvd_104/uxvrcv 144 tmrin1 25 rxd_hu 65 a12 105 drq1 145 int6 26 txd_hu 66 ad5 106 v cc 146 int7 27 v cc 67 ad13 107 int0 147 int8/pwd 28 ad0 68 v cc 108 v ss 148 v cc 29 ad8 69 a13 109 int1 149 dce_tclk_c/ pcm_fsc_c 30 a0 70 a14 110 int2 150 dce_rclk_c/ pcm_clk_c 31 a1 71 v ss 111 int3 151 dce_rtr_c 32 a2 72 v ss _a 112 int4 152 dce_cts_c / pcm_tsc_c 33 v ss 73 x1 113 int5 153 dce_rxd_c/ pcm_rxd_c 34 ad1 74 x2 114 res 154 dce_txd_c/ pcm_txd_c 35 ad9 75 usbx1 115 nmi 155 v ss 36 a3 76 usbx2 116 dce_tclk_a/ gci_fsc_a/ pcm_fsc_a 156 rtr_u / dce_rclk_d/ pcm_clk_d 37 a4 77 v cc _a 117 dce_rclk_a / gci_dcl_a/ pcm_clk_a 157 cts_u / dce_tclk_d/ pcm_fsc_d
am186?cc communications controller data sheet 11 38 ad2 78 v cc 1 1 8 dce_rxd_a/gci_dd_a/ pcm_rxd_a 158 rxd_u/dce_rxd_d/ pcm_rxd_d 39 ad10 79 v cc _ u s b 1 1 9 dce_txd_a/gci_du_a/ pcm_txd_a 159 txd_u/dce_txd_d/ pcm_txd_d 40 v cc 80 usbdC/udmns 120 v cc 160 v cc notes: 1. see table 29, pios sorted by pio number, on page a-8 for pios sorted by pio number. table 2. pqfp pin assignmentssorted by signal name 1 signal name pin no. signal name pin no. signal name pin no. signal name pin no. a0 30 clkout 60 mcs3 /ras1 129 usbdC/udmns 80 a1 31 cts_hu /dce_cts_d / pcm_tsc_d 24 nmi 115 usbx1 75 a2 32 cts_u /dce_tclk_d/ pcm_fsc_d 157 pcs0 {usbsel1} 5 usbx2 76 a3 36 dce_cts_a /pcm_tsc_a 123 pcs1 {usbsel2} 6 v cc 12 a4 37 dce_cts_b / pcm_tsc_b 137 pcs2 7v cc 27 a5 42 dce_cts_c /pcm_tsc_c 152 pcs3 8v cc 40 a6 43 dce_rclk_a/ gci_dcl_a/pcm_clk_a 117 pcs4 {clksel2} 9 v cc 48 a7 44 dce_rclk_b/ pcm_clk_b 135 pcs5 10 v cc 59 a8 45 dce_rclk_c/pcm_clk_c 150 pcs6 11 v cc 68 a9 49 dce_rtr_a 122 pcs7 13 v cc 78 a10 50 dce_rtr_b 136 qs0 62 v cc 91 a11 64 dce_rtr_c 151 qs1 63 v cc 106 a 1 2 6 5 dce_rxd_a/gci_dd_a/ pcm_rxd_a 118 rd 97 v cc 120 a13 69 dce_rxd_b/ pcm_rxd_b 138 res 114 v cc 125 a14 70 dce_rxd_c/ pcm_rxd_c 153 resout 58 v cc 133 a15 84 dce_tclk_a/ gci_fsc_a/pcm_fsc_a 116 rsvd_104/uxvrcv 104 v cc 148 a16 85 dce_tclk_b/ pcm_fsc_b 134 rsvd_103/uxvoe 103 v cc 160 a17 88 dce_tclk_c/ pcm_fsc_c 149 rsvd_102/utxdmns 102 v cc _a 77 a 18 89 dce_txd_a/gci_du_a/ pcm_txd_a 119 rsvd_101/utxdpls 101 v cc _usb 79 a19 90 dce_txd_b/ pcm_txd_b 139 rtr_hu /dce_rtr_d 23 v ss 1 ad0 28 dce_txd_c/ pcm_txd_c 154 rtr_u /dce_rclk_d/ pcm_clk_d 156 v ss 21 ad1 34 den /ds 18 rxd_hu 25 v ss 33 ad2 38 drq0 124 rxd_u/dce_rxd_d/ pcm_rxd_d 158 v ss 41 ad3 46 drq1 105 s0 {usbxcvr }57v ss 53 ad4 51 dt/r 17 s1 56 v ss 61 ad5 66 hlda {clksel1} 98 s2 55 v ss 71 ad6 86hold 99s6 54v ss 83 ad7 92 int0 107 sclk 3 v ss 100 ad8 29 int1 109 sdata 4 v ss 108 ad9 35 int2 110 sden 2 v ss 121 ad10 39 int3 111 srdy 15 v ss 130 table 1. pqfp pin assignmentssorted by pin number 1 (continued) pin no. nameleft side pin no. namebottom side pin no. nameright side pin no. nametop side
12 am186?cc communications controller data sheet ad11 47 int4 112 tmrin0 142 v ss 140 ad12 52 int5 113 tmrin1 144 v ss 155 ad13 67 int6 145 tmrout0 141 v ss _a 72 ad14 87 int7 146 tmrout1 143 v ss _usb 82 ad15 93 int8/pwd 147 txd_hu 26 whb 95 ale 19 lcs /ras0 131 txd_u/dce_txd_d/ pcm_txd_d 159 wlb 96 ardy 14 mcs0 {ucsx8 } 126 uclk/usbsof/usbsci 22 wr 16 bhe {aden }20mcs1 /cas1 127 ucs {once } 132 x1 73 bsize8 94 mcs2 /cas0 128 usbd+/udpls 81 x2 74 notes: 1. for pios sorted by signal name, refer to table 30, pios sorted by signal name, on page a-9. table 2. pqfp pin assignmentssorted by signal name 1 (continued) signal name pin no. signal name pin no. signal name pin no. signal name pin no.
am186?cc communications controller data sheet 13 signal descriptions table 4 on page 14 contains a description of the AM186CC controller signals. table 3 describes the terms used in table 4. the signals are organized alphabetically within the following functional groups: n bus interface/general-purpose dma request (page 14) n clocks/reset/watchdog timer (page 17) n no connects (page 18) n power and ground (page 19) n debug support (page 19) n chip selects (page 19) n dram (page 20) n interrupts (page 21) n programmable i/o (pios) (page 22) n programmable timers (page 22) n asynchronous serial ports (uart and high-speed uart) (page 22) n synchronous serial interface (ssi) (page 23) n hdlc synchronous communications: channels aCd for data communications equipment (dce), pulse-code modulation (pcm), and general circuit interface (gci) interfaces (page 23) n universal serial bus (usb) (page 26) for pinstraps, refer to table 31, reset configuration pins (pinstraps), on page a-10. table 3. signal description table definitions term definition general terms [ ] pin alternate function; a pin defaults to the signal named without the brackets { } reset configuration pin (pinstrap) pin refers to the physical wire reset an external or power-on reset is caused by asserting res . an internal reset is initiated by the watchdog timer. a system reset is one that resets the AM186CC controller (the cpu plus the internal peripherals) as well as any external peripherals connected to resout. an external reset always causes a system reset; an internal reset can optionally cause a system reset. signal refers to the electrical signal that flows across a pin signal a line over a signal name indicates that the signal is active low; a signal name without a line is active high. signal types b bidirectional hhigh ls programmable to hold last state of pin o totem pole output od open drain output od-o open drain output or totem pole output pd internal pulldown resistor pu internal pullup resistor sti schmitt trigger input sti-od schmitt trigger input or open drain output ts three-state output
14 am186?cc communications controller data sheet table 4. signal descriptions signal name multiplexed signal(s) type description bus interface/general-purpose dma request a19Ca0 o address bus supplies nonmultiplexed memory or i/o addresses to the system one half of a clkout period earlier than the multiplexed address and data bus (ad15Cad0). during bus-hold or reset conditions, the address bus is three- stated with pulldowns. when the lower or upper chip-select regions are configured for dram mode, the a19Ca0 bus provides the row and column addresses at the appropriate times. the upper and lower memory chip-select ranges can be individually configured for dram mode. ad15Cad0 b address and data bus time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an address to the system during the first period of a bus cycle (t 1 ). it transmits (write cycle) or receives (read cycle) data to or from the system during the remaining periods of that cycle (t2, t3, and t4). the address phase of these pins can be disabledsee the {aden } pin description in table 31, reset configuration pins (pinstraps), on page a-10. during a reset condition, the address and data bus is three-stated with pulldowns, and during a bus hold it is three-stated. in addition, during a reset the state of the address and data bus pins (ad15C ad0) is latched into the reset configuration (rescon) register. this feature can be used to provide software with information about the external system at reset time. ale [pio33] o address latch enable indicates to the system that an address appears on the address and data bus (ad15Cad0). the address is guaranteed valid on the falling edge of ale. ale is three-stated and has a pulldown resistor during bus-hold or reset conditions. ardy [pio8] sti asynchronous ready is a true asynchronous ready that indicates to the AM186CC controller that the addressed memory space or i/o device will complete a data transfer. the ardy pin is asynchronous to clkout and is active high. to guarantee the number of wait states inserted, ardy or srdy must be synchronized to clkout. if the falling edge of ardy is not synchronized to clkout as specified, an additional clock period can be added. to always assert the ready condition to the microcontroller, tie ardy and srdy high. if the system does not use ardy, tie the pin low to yield control to srdy.
am186?cc communications controller data sheet 15 bhe [pio34] {aden } o bus high enable: during a memory access, bhe and the least-significant address bit (ad0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe and ad0 pins are encoded as follows: bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not require latching. bhe is three-stated with a pullup during bus-hold and reset conditions. wlb and whb implement the functionality of bhe and ad0 for high and low byte write enables, and they have timing appropriate for use with the nonmultiplexed bus interface. bhe also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a refresh cycle is indicated when both bhe and ad0 are high. during refresh cycles, the ad bus is driven during the t 1 phase and three-stated during the t 2 , t 3 , and t 4 phases. the value driven on the a bus is undefined during a refresh cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. bsize8 o bus size 8 is asserted during t 1 Ct 4 to indicate an 8-bit cycle, or is deasserted to indicate a 16-bit cycle. den [ds ] [pio30] o data enable supplies an output enable to an external data-bus transceiver. den is asserted during memory and i/o cycles. den is deasserted when dt/r changes state. den is three-stated with a pullup during bus-hold or reset conditions. [ds ]den pio30 o data strobe provides a signal where the write cycle timing is identical to the read cycle timing. when used with other control signals, [ds ] provides an interface for 68k-type peripherals without the need for additional system interface logic. when [ds ] is asserted, addresses are valid. when [ds ] is asserted on writes, data is valid. when [ds ] is asserted on reads, data can be driven on the ad bus. following a reset, this pin is configured as den . the pin is then configured by software to operate as [ds ]. dt/r [pio29] o data transmit or receive indicates which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the AM186CC controller transmits data. when this pin is deasserted low, the controller receives data. dt/r is three-stated with a pullup during a bus-hold or reset condition. drq1 [drq0] pio9 sti sti dma requests 1 and 0 indicate to the AM186CC controller that an external device is ready for a dma channel to perform a transfer. drq1C[drq0] are level-triggered and internally synchronized. drq1C[drq0] are not latched and must remain active until serviced. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description data byte encoding bhe ad0 type of bus cycle 00word transfer 0 1 high byte transfer (bits 15C8) 1 0 low byte transfer (bits 7C0) 11refresh
16 am186?cc communications controller data sheet hlda {clksel1} o bus-hold acknowledge is asserted to indicate to an external bus master that the AM186CC controller has relinquished control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress, then relinquishes control of the bus to the external bus master by asserting hlda and three-stating s 2 Cs 0 , ad15Cad0, s6, and a19Ca0. the following are also three-stated and have pullups: ucs , lcs , mcs 3 Cmcs 0 , pcs 7 Cpcs 0 , den , rd , wr , bhe , whb , wlb , and dt/r . ale is three-stated and has a pulldown. when the external bus master has finished using the local bus, it indicates this to the AM186CC controller by deasserting hold. the controller responds by deasserting hlda. if the AM186CC controller requires access to the bus (for example, for refresh), the controller deasserts hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the controller access to the bus. see the timing diagrams for bus hold on page 70. hold sti bus-hold request indicates to the AM186CC controller that an external bus master needs control of the local bus. the AM186CC controllers hold latency timethe time between hold request and hold acknowledgeis a function of the activity occurring in the processor when the hold request is received. a hold request is second only to dram refresh requests in priority of activity requests received by the processor. this implies that if a hold request is received just as a dma transfer begins, the hold latency can be as great as four bus cycles. this occurs if a dma word transfer operation is taking place from an odd address to an odd address. this is a total of 16 clock cycles or more if wait states are required. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. hold latency is also potentially increased by dram refreshes. the board designer is responsible for properly terminating the hold input. for more information, see the hlda pin description. rd o read strobe indicates to the system that the AM186CC controller is performing a memory or i/o read cycle. rd is guaranteed to not be asserted before the address and data bus is three-stated during the address-to-data transition. rd is three-stated with a pullup during bus-hold or reset conditions. s6 o bus cycle status bit 6: this signal is asserted during t 1 Ct 4 to indicate a dma- initiated bus cycle or a refresh cycle. s6 is three-stated during bus hold and three-stated with a pulldown during reset. srdy [pio35] sti synchronous ready indicates to the AM186CC controller that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkout. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to always assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
am186?cc communications controller data sheet 17 s2 s1 s0 {usbxcvr } o bus cycle status 2C0 indicate to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator, and s 1 can be used as a data transmit or receive indicator. s 2 Cs 0 are three-stated during bus hold and three-stated with a pullup during reset. the s 2 Cs 0 pins are encoded as follows: whb wlb o o write high byte and write low byte indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical and of bhe and wr . this pin is three-stated with a pullup during bus-hold or reset conditions. wlb is asserted with ad7Cad0. wlb is the logical and of ad0 and wr . this pin is three-stated with a pullup during bus-hold or reset conditions. wr [pio15] o write strobe indicates to the system that the data on the bus is to be written to a memory or i/o device. wr is three-stated with a pullup during bus-hold or reset conditions. clocks/reset/watchdog timer clkout o clock output supplies the clock to the system. depending on the values of the cpu mode select pinstraps, {clksel1} and {clksel2}, clkout operates at either the pll frequency or the source input frequency during pll bypass mode. (see table 31, reset configuration pins (pinstraps), on page a-10.) clkout remains active during bus-hold or reset conditions. the disclk bit in the syscon register can be set to disable the clkout signal. refer to the am186?cc/ch/cu microcontrollers register set manual (order #21916). all synchronous ac timing specifications not associated with ssi, hdlcs, uarts, and the usb are synchronous to clkout. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description bus status pins s2 s1 s0 bus cycle 0 0 0 reserved 0 0 1 read data from i/o 0 1 0 write data to i/o 011halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive)
18 am186?cc communications controller data sheet res sti reset requires the AM186CC controller to perform a reset. when res is asserted, the controller immediately terminates its present activity, clears its internal logic, and on the deassertion of res , transfers cpu control to the reset address ffff0h. res must be asserted for at least 1 ms to allow the internal circuits to stabilize. res can be asserted asynchronously to clkout because res is synchronized internally. for proper initialization, v cc must be within specifications, and clkout must be stable for more than four clkout periods during which res is asserted. if res is asserted while the watchdog timer is performing a watchdog-timer reset, the external reset takes precedence over the watchdog-timer reset. this means that the resout signal asserts as with any external reset and the wdtcon register will not have the rstflag bit set. in addition, the controller will exit reset based on the external reset timing, i.e., 4.5 clocks after the deassertion of res rather than 2 16 clocks after the watchdog timer timeout occurred. the AM186CC controller begins fetching instructions approximately 6.5 clkout periods after res is deasserted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network. resout o reset out indicates that the AM186CC controller is being reset (either externally or internally), and the signal can be used as a system reset to reset any external peripherals connected to resout. during an external reset, resout remains active (high) for two clocks after res is deasserted. the controller exits reset and begins the first valid bus cycle approximately 4.5 clocks after res is deasserted. [uclk] [usbsof] [usbsci] pio21 sti uart clock can be used instead of the processor clock as the source clock for either the uart or the high-speed uart. the source clock for the uart and the high-speed uart are selected independently and both can use the same source. usbx1 usbx2 sti o usb controller crystal input (usbx1) and usb controller crystal output (usbx2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal usb oscillator circuit. if the cpu crystal is used to generate the usb clock, usbx1 must be pulled down. x1 x2 sti o cpu crystal input (x1) and cpu crystal output (x2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal oscillator circuit. if an external oscillator is used, inject the signal directly into x1 and leave x2 floating. pinstraps (see table 31, reset configuration pins (pinstraps), on page a-10.) reserved rsvd_101 rsvd_102 rsvd_103 rsvd_104 utxdpls utxdmns uxvoe uxvrcv rsvd_101Crsvd_104 are reserved unless pinstrap {usbxcvr } is sampled low on the rising edge of reset. when reserved, these pins should not be connected. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
am186?cc communications controller data sheet 19 power and ground v cc (15) sti digital power supply pins supply power (+3.3 0.3 v) to the AM186CC controller logic. v cc _a (1) sti analog power supply pin supplies power (+3.3 0.3 v) to the oscillators and plls. v cc _usb (1) sti usb power supply pin supplies power (+3.3 0.3 v) to the usb block. v ss (15) sti digital ground pins connect the AM186CC controller logic to the system ground. v ss _a (1) sti analog ground pin connects the oscillators and plls to the system ground. v ss _usb (1) sti usb ground pin connects the usb block to the system ground. debug support qs1Cqs0 o queue status 1C0 values provide information to the system concerning the interaction of the cpu and the instruction queue. the pins have the following meanings: the following signals are also used by emulators: a19Ca0, ad15Cad0, {aden }, ale, ardy, bhe , bsize8 , cas1 Ccas0 , clkout, {clksel2 Cclksel1 }, hlda, hold, lcs , mcs3 Cmcs0 , nmi, {once }, qs1Cqs0, ras1 Cras0 , rd , res , resout, s2 Cs0 , s6, srdy, ucs , {ucsx8 }, v cc , whb , wlb , wr . see the am186?cc/ch/cu microcontrollers users manual , order #21914, for more information. chip selects lcs [ras0 ]o lower memory chip select indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbyte. lcs can be configured for 8- bit or 16-bit bus size. lcs is three-stated with a pullup resistor during bus-hold or reset conditions. [mcs3 ] mcs2 mcs1 [mcs0 ] [ras1 ] pio5 [cas0 ] [cas1 ] {ucsx8 } pio4 o midrange memory chip selects 3C0 indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. the midrange chip selects can be configured for 8-bit or 16-bit bus size. the midrange chip selects are three-stated with pullup resistors during bus-hold or reset conditions. [mcs0 ] can be programmed as the chip select for the entire middle chip select address range. unlike the ucs and lcs chip selects that operate relative to the earlier timing of the nonmultiplexed a address bus, the mcs outputs assert with the multiplexed ad address and data bus timing. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description queue status pins qs1 qs0 queue operation 0 0 none 0 1 first opcode byte fetched from queue 1 0 queue was initialized 1 1 subsequent byte fetched from queue
20 am186?cc communications controller data sheet [pcs7 ] [pcs6 ] [pcs5 ] [pcs4 ] pcs3 pcs2 pcs1 pcs0 pio31 pio32 pio2 pio3 {clksel2} [pio14] {usbsel2} [pio13] {usbsel1} o peripheral chip selects 7C0 indicate to the system that an access is in progress to the corresponding region of the peripheral address block (either i/o or memory address space). the base address of the peripheral address block is programmable. pcs7 Cpcs0 are three-stated with pullup resistors during bus- hold or reset conditions. unlike the ucs and lcs chip selects that operate relative to the earlier timing of the nonmultiplexed a address bus, the pcs outputs assert with the multiplexed ad address and data bus timing. ucs {once }o upper memory chip select indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is three-stated with a weak pullup during bus-hold or reset conditions. the ucs can be configured for an 8-bit or 16-bit bus size out of reset. for additional information, see the {ucsx8 } pin description in table 31, reset configuration pins (pinstraps), on page a-10. after reset, ucs is active for the 64-kbyte memory range from f0000h to fffffh, including the reset address of ffff0h. dram [cas1 ] [cas0 ] mcs1 mcs2 o column address strobes 1C0 : when either the upper or lower chip select regions are configured for dram, these pins provide the column address strobe signals to the dram. the cas signals can be used to perform byte writes in a manner similar to whb and wlb , respectively (i.e., [cas0 ] corresponds to the low byte (wlb ) and [cas1 ] corresponds to the high byte (whb )). [ras1 ][mcs3 ] pio5 o row address strobe 1 : when the upper chip select region is configured to dram, this pin provides the row address strobe signal to the upper dram bank. [ras0 ]lcs o row address strobe 0 : when the lower chip select region is configured to dram, this pin provides the row address strobe signal to the lower dram bank. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
am186?cc communications controller data sheet 21 interrupts nmi sti nonmaskable interrupt indicates to the AM186CC controller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and cannot be masked. the controller always transfers program execution to the location specified by the nonmaskable interrupt vector in the controllers interrupt vector table when nmi is asserted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request registers. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the interrupt flag (if) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable interrupts are re-enabled by software in the nmi interrupt service routine (for example, via the sti instruction), the fact that an nmi is currently in service does not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt service routine for nmi should not enable the maskable interrupts. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi pin must be asserted for at least one clkout period. the board designer is responsible for properly terminating the nmi input. [int8] [int7] [int6] int5Cint0 [pwd] pio6 pio7 pio19 sti sti sti sti maskable interrupt requests 8C0 indicate to the AM186CC controller that an external interrupt request has occurred. if the individual pin is not masked, the controller transfers program execution to the location specified by the associated interrupt vector in the controllers interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. the interrupt polarity is programmable. to guarantee interrupt recognition for edge-triggered interrupts, the user should hold the interrupt source for a minimum of five system clocks. a second interrupt from the same source is not recognized until after an acknowledge of the first. the board designer is responsible for properly terminating the int8Cint0 inputs. also configurable as interrupts are pio5, pio15, pio27, pio29, pio30, pio33, pio34, and pio35. (see the am186?cc/ch/cu microcontrollers users manual , order #21914 for more information.) table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
22 am186?cc communications controller data sheet programmable i/o (pios) pio47Cpio0 (for multiplexed signals see table 29, pios sorted by pio number, on page a-8 and table 30, pios sorted by signal name, on page a-9.) b shared programmable i/o pins can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. after a reset, the pio pins default to various configurations. the column entitled pin configuration following system reset in table 29 on page a-8 and table 30 on page a-9 lists the defaults for the pios. most of the pio pins are configured as pio inputs with pullup after reset. see table 35 on page a-12 for detailed termination information for all pins. the system initialization code must reconfigure any pio pins as required. pio5, pio15, pio27, pio29, pio30, and pio33Cpio35 are capable of generating an interrupt on the shared interrupt channel 14. the multiplexed signals ale, ardy, bhe , den , dt/r , pcs1 Cpcs0 , srdy, and wr default to non-pio operation at reset. the following pio signals are multiplexed with alternate signals that can be used by emulators: pio8, pio15, pio33, pio34, and pio35. consider any emulator requirements for the alternate signals before using these pins as pios. programmable timers [pwd] [int8] pio6 sti pulse-width demodulator: if pulse-width demodulation is enabled, [pwd] processes a signal through the schmitt trigger input. [pwd] is used internally to drive [tmrin0] and [int8], and [pwd] is inverted internally to drive [tmrin1] and an additional internal interrupt. if interrupts are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating [pwd] signal can be calculated by comparing the values in timer 0 and timer 1. in pwd mode, the signals [tmrin0]/pio27 and [tmrin1]/pio0 can be used as pios. if they are not used as pios they are ignored internally. the additional internal interrupt used in pwd mode uses the same interrupt channel as [int7]. if [int7] is to be used, it must be assigned to the shared interrupt channel. [tmrin1] [tmrin0] pio0 pio27 sti sti timer inputs 1C0 supply a clock or control signal to the internal AM186CC controller timers. after internally synchronizing a low-to-high transition on [tmrin1]C[tmrin0], the microcontroller increments the timer. [tmrin1]C [tmrin0] must be tied high if not being used. when pio is enabled for one or both, the pin is pulled high internally. [tmrin1]C[tmrin0] are driven internally by [int8]/[pwd] when pulse-width demodulation functionality is enabled. the [tmrin1]C[tmrin0] pins can be used as pios when pulse-width demodulation is enabled. [tmrout1] [tmrout0] pio1 pio28 o o timer outputs 1C0 supply the system with either a single pulse or a continuous waveform with a programmable duty cycle. [tmrout1]C[tmrout0] are three- stated during bus-hold or reset conditions. asynchronous serial ports (uart and high-speed uart) uart [rxd_u] dce_rxd_d [pcm_rxd_d] pio26 sti receive data uart is the asynchronous serial receive data signal that supplies data from the asynchronous serial port to the microcontroller. [txd_u] [dce_txd_d] [pcm_txd_d] pio20 o transmit data uart is the asynchronous serial transmit data signal that supplies data to the asynchronous serial port from the microcontroller table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
am186?cc communications controller data sheet 23 [cts_u ] [dce_tclk_d] [pcm_fsc_d] pio24 sti clear-to-send uart provides the clear-to-send signal from the asynchronous serial port when hardware flow control is enabled for the port. the [cts_u ] signal gates the transmission of data from the serial port transmit shift register. when [cts_u ] is asserted, the transmitter begins transmission of a frame of data, if any is available. if [cts_u ] is deasserted, the transmitter holds the data in the serial port transmit shift register. the value of [cts_u ] is checked only at the beginning of the transmission of the frame. [cts_u ] and [rtr_u ] form the hardware handshaking interface for the uart. [rtr_u ] dce_rclk_d [pcm_clk_d] pio25 o ready-to-receive uart provides the ready-to-receive signal for the asynchronous serial port when hardware flow control is enabled for the port. the [rtr_u ] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [cts_u ] and [rtr_u ] form the hardware handshaking interface for the uart. high-speed uart [rxd_hu] pio16 sti receive data high-speed uart is the asynchronous serial receive data signal that supplies data from the high-speed serial port to the controller. txd_hu o transmit data high-speed uart is the asynchronous serial transmit data signal that supplies data to the high-speed serial port from the microcontroller. [cts_hu ] [dce_cts_d ] [pcm_tsc_d ] pio46 sti clear-to-send high-speed uart provides the clear-to-send signal from the high-speed asynchronous serial port when hardware flow control is enabled for the port. the [cts_hu ] signal gates the transmission of data from the serial port transmit shift register. when [cts_hu ] is asserted, the transmitter begins transmission of a frame of data, if any is available. if [cts_hu ] is deasserted, the transmitter holds the data in the serial port transmit shift register. the value of [cts_hu ] is checked only at the beginning of the transmission of the frame. [cts_hu ] and [rtr_hu ] form the hardware handshaking interface for the high- speed uart. [rtr_hu ] [dce_rtr_d ] pio47 o ready-to-receive high-speed uart provides the ready-to-receive signal to the high-speed asynchronous serial port when hardware flow control is enabled for the port. the [rtr_hu ] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [cts_hu ] and [rtr_hu ] form the hardware handshaking interface for the high-speed uart. synchronous serial interface (ssi) [sclk] pio11 o serial clock provides the clock for the synchronous serial interface to allow synchronous transfers between the AM186CC controller and a slave device. [sdata] pio12 b serial data is used to transmit and receive data between the AM186CC controller and a slave device on the synchronous serial interface. [sden] pio10 o serial data enable enables data transfers on the synchronous serial interface. high-level data link control synchronous communication interfaces hdlc channel a (dce) dce_rxd_a [gci_dd_a] [pcm_rxd_a] sti dce receive data channel a is the serial data input pin for the channel a dce interface. dce_txd_a [gci_du_a] [pcm_txd_a] od-o dce transmit data channel a is the serial data output pin for the channel a dce interface. dce_rclk_a [gci_dcl_a] [pcm_clk_a] sti dce receive clock channel a provides the receive clock to the channel a dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_tclk_a pin externally. the dce function is the default at reset, so the board designer is responsible for properly terminating the dce_rclk_a input. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
24 am186?cc communications controller data sheet dce_tclk_a [gci_fsc_a] [pcm_fsc_a] sti dce transmit clock channel a provides the transmit clock to the channel a dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_rclk_a pin externally. the dce function is the default at reset, so the board designer is responsible for properly terminating the dce_tclk_a input. [dce_cts_a ] [pcm_tsc_a ] pio17 sti dce clear to send channel a indicates to the channel a dce interface that an external serial interface is ready to receive data. [dce_cts_a ] and [dce_rtr_a ] provide the handshaking for dce channel a. [dce_rtr_a ]pio18 o dce ready to receive channel a indicates to an external serial interface that the internal channel a dce interface is ready to accept data. [dce_cts_a ] and [dce_rtr_a ] provide the handshaking for the channel a dce interface. hdlc channel b (dce) [dce_rxd_b] [pcm_rxd_b] pio36 sti dce receive data channel b is the serial data input pin for the channel b dce interface. [dce_txd_b] [pcm_txd_b] pio37 od-o dce transmit data channel b is the serial data output pin for the channel b dce interface. [dce_rclk_b] [pcm_clk_b] pio40 sti dce receive clock channel b provides the receive clock to the channel b dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_tclk_b] pin externally. [dce_tclk_b] [pcm_fsc_b] pio41 sti dce transmit clock channel b provides the transmit clock to the channel b dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_rclk_b] pin externally. [dce_cts_b ] [pcm_tsc_b ] pio38 sti dce clear to send channel b indicates to the channel b dce interface that an external serial interface is ready to receive data. [dce_cts_b ] and [dce_rtr_b ] provide the handshaking for the channel b dce interface. [dce_rtr_b ] pio39 o dce ready to receive channel b indicates to an external serial interface that the internal channel b dce interface is ready to accept data. [dce_cts_b ] and [dce_rtr_b ] provide the handshaking for the channel b dce interface. hdlc channel c (dce) [dce_rxd_c] [pcm_rxd_c] pio42 sti dce receive data channel c is the serial data input pin for the channel c dce interface. [dce_txd_c] [pcm_txd_c] pio43 od-o dce transmit data channel c is the serial data output pin for the channel c dce interface. [dce_rclk_c] [pcm_clk_c] pio22 sti dce receive clock channel c provides the receive clock to the channel c dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_tclk_c] pin externally. [dce_tclk_c] [pcm_fsc_c] pio23 sti dce transmit clock channel c provides the transmit clock to the channel c dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_rclk_c] pin externally. [dce_cts_c ] [pcm_tsc_c ] pio44 sti dce clear to send channel c indicates to the channel c dce interface that an external serial interface is ready to receive data. [dce_cts_c ] and [dce_rtr_c ] provide the handshaking for the channel c dce interface. [dce_rtr_c ] pio45 o dce ready to receive channel c indicates to an external serial interface that the internal channel c dce is ready to accept data. [dce_cts_c ] and [dce_rtr_c ] provide the handshaking for the channel c dce interface. hdlc channel d (dce) dce_rxd_d [rxd_u] (uart) [pcm_rxd_d] pio26 sti dce receive data channel d is the serial data input pin for the channel d dce interface. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
am186?cc communications controller data sheet 25 [dce_txd_d] [txd_u] (uart) [pcm_txd_d] pio20 od-o dce transmit data channel d is the serial data output pin for the channel d dce interface. dce_rclk_d [rtr_u ] (uart) [pcm_clk_d] pio25 sti dce receive clock channel d provides the receive clock to the channel d dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the [dce_tclk_d] pin externally. [dce_tclk_d] [cts_u ] (uart) [pcm_fsc_d] pio24 sti dce transmit clock channel d provides the transmit clock to the channel d dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_rclk_d pin externally. [dce_cts_d ] [cts_hu ] (high- speed uart) [pcm_tsc_d ] pio46 sti dce clear to send channel d indicates to the channel d dce interface that an external serial interface is ready to receive data. [dce_cts_d ] and [dce_rtr_d ] provide the handshaking for dce channel d. [dce_rtr_d ] [rtr_hu ] (high- speed uart) pio47 o dce ready to receive channel d indicates to an external serial interface that the internal channel d dce interface is ready to accept data. [dce_cts_d ] and [dce_rtr_d ] provide the handshaking for the channel d dce interface. hdlc channel a (pcm) [pcm_rxd_a] dce_rxd_a [gci_dd_a] sti pcm receive data channel a is the serial data input pin for the channel a pcm highway interface. [pcm_txd_a] dce_txd_a [gci_du_a] o-ls- od pcm transmit data channel a is the serial data output pin for the channel a pcm highway interface. [pcm_clk_a] dce_rclk_a [gci_dcl_a] sti pcm clock is the single transmit and receive data clock pin for the channel a pcm highway interface. [pcm_fsc_a] dce_tclk_a [gci_fsc_a] sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel a pcm highway interface. [pcm_tsc_a ] [dce_cts_a ] pio17 od pcm time slot control a enables an external buffer device when channel a pcm highway data is present on the [pcm_txd_a] output pin in pcm highway mode. hdlc channel b (pcm) [pcm_rxd_b] [dce_rxd_b] pio36 sti pcm receive data channel b is the serial data input pin for the channel b pcm highway interface. [pcm_txd_b] [dce_txd_b] pio37 o-ls- od pcm transmit data channel b is the serial data output pin for the channel b pcm highway interface. [pcm_clk_b] [dce_rclk_b] pio40 sti pcm clock is the single transmit and receive data clock pin for the channel b pcm highway interface. [pcm_fsc_b] [dce_tclk_b] pio41 sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel b pcm highway interface. [pcm_tsc_b ] [dce_cts_b ] pio38 od pcm time slot control b enables an external buffer device when channel b pcm highway data is present on the [pcm_txd_b] output pin in pcm highway mode. hdlc channel c (pcm) [pcm_rxd_c] [dce_rxd_c] pio42 sti pcm receive data channel c is the serial data input pin for the channel c pcm highway interface. [pcm_txd_c] [dce_txd_c] pio43 o-ls- od pcm transmit data channel c is the serial data output pin for the channel c pcm highway interface. [pcm_clk_c] [dce_rclk_c] pio22 sti- o pcm clock: for pcm highway operation, [pcm_clk_c] is the single transmit and receive data clock input pin for the channel c pcm highway interface. [pcm_clk_c] becomes a clock source output when the gci to pcm highway clock and frame synchronization conversion are enabled. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
26 am186?cc communications controller data sheet [pcm_fsc_c] [dce_tclk_c] pio23 b pcm frame synchronization clock: for pcm highway operation, [pcm_fsc_c] provides the frame synchronization clock input (usually 8 khz) for the channel c pcm highway interface. [pcm_fsc_c] becomes a frame synchronization source output when the gci to pcm highway clock and frame synchronization conversion are enabled. [pcm_tsc_c ] [dce_cts_c ] pio44 od pcm time slot control c enables an external buffer device when channel c pcm highway data is present on the [pcm_txd_c] output pin in pcm highway mode. hdlc channel d (pcm) [pcm_rxd_d] [rxd_u] (uart) dce_rxd_d pio26 sti pcm receive data channel d is the serial data input pin for the channel d pcm highway interface. [pcm_txd_d] [txd_u] (uart) [dce_txd_d] pio20 o-ls- od pcm transmit data channel d is the serial data output pin for the channel d pcm highway interface. [pcm_clk_d] [rtr_u ] (uart) dce_rclk_d pio25 sti pcm clock is the single transmit and receive data clock pin for the channel d pcm highway interface. [pcm_fsc_d] [cts_u ] (uart) [dce_tclk_d] pio24 sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel d pcm highway interface. [pcm_tsc_d ] [cts_hu ] (high- speed uart) [dce_cts_d ] pio46 od pcm time slot control d enables an external buffer device when channel d pcm highway data is present on the [pcm_txd_d] output pin in pcm highway mode. hdlc channel a (gci) [gci_dd_a] dce_rxd_a [pcm_rxd_a] b- od gci data downstream is the serial data input pin for the channel a gci interface. [gci_du_a] dce_txd_a [pcm_txd_a] b- od gci data upstream is the serial data output pin for the channel a gci interface. [gci_dcl_a] dce_rclk_a [pcm_clk_a] sti gci data clock is the single transmit and receive channel a gci data clock input generated by an upstream device. the data clock frequency must be twice the data rate. [gci_fsc_a] dce_tclk_a [pcm_fsc_a] sti gci frame synchronization clock provides the 8-khz frame synchronization clock input for the channel a gci interface generated by an upstream device. universal serial bus [udmns] [udpls] usbdC usbd+ sti sti usb external transceiver gated differential plus and usb external transceiver gated differential minus are inputs from the external usb transceiver used to detect single-ended zero and error conditions. the signals have the following meanings: usbd+ usbdC [udpls] [udmns] b b usb differential plus and usb differential minus form the bidirectional electrical data interface for the usb port. the pins form a differential pair that can be connected to a physical usb connector without an external transceiver. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description usb external transceiver signals udpls udmns status 0 0 single-ended zero (se0) 0 1 full speed 10reserved 1 1 error
am186?cc communications controller data sheet 27 [usbsci] [uclk] [usbsof] pio21 sti usb sample clock input is used to synchronize an external clock to the internal usb peripheral controller for isochronous transfers. [usbsof] [uclk] [usbsci] pio21 o usb start of frame is a 1-khz frame pulse used to synchronize usb isochronous transfers to an external device on a frame-by-frame basis. utxdmns rsvd_102 o usb external transceiver differential minus is an output that drives the external transceiver differential driver minus input. utxdpls rsvd_101 o usb external transceiver differential plus is an output that drives the external transceiver differential driver plus input. uxvoe rsvd_103 o usb external transceiver transmit output enable is an output that enables the external transceiver. uxvoe signals the external transceiver that usb data is being output by the AM186CC usb controller. when low, this pin enables the transceiver output; when high, this pin enables the receiver. uxvrcv rsvd_104 sti usb external transceiver differential receiver is a data input received from the external transceiver differential receiver. table 4. signal descriptions (continued) signal name multiplexed signal(s) type description
28 am186?cc communications controller data sheet architectural overview the architectural goal of the AM186CC microcontroller is to provide comprehensive communications features on a processor running the widely known x86 instruction set. the AM186CC microcontroller combines four hdlc channels, a usb peripheral controller, and general communications peripherals with the am186 microcontroller. this highly integrated microcontroller provides system cost and performance advantages for a wide range of communications applications. figure 1 is a block diagram of the AM186CC microcontroller, followed by sections providing an overview of the features of the AM186CC microcontroller. figure 1. AM186CC controller block diagram detailed description n universal serial bus (usb) peripheral controller works with a wide variety of usb devices C implements high-speed 12-mbit/s device function C allows an unlimited number of device descriptors C supports a total of six endpoints: one control endpoint; one interrupt endpoint; four data endpoints that can be either bulk or isochronous, in or out C two data endpoints have 16-byte fifos; two data endpoints have 64-byte fifos C fully integrated differential driver directly supports the usb interface (d+, dC) C specialized hardware supports adaptive isochronous data streams C general-purpose dma and smartdma? channels supported n four independent high-level data link control (hdlc) channels support a wide range of external interfaces C external interface connection for hdlcs can be pcm highway, gci, or raw dce C data rate of up to 10 mbit/s C receive and transmit fifos C support for hdlc, synchronous data link control (sdlc), line access procedure balanced (lap-b), line access procedure d (lap-d), point-to-point protocol (ppp), and v.120 (support of v.110 in transparent mode) C two dedicated buffer descriptor ring smartdma channels per hdlc C one independent time-slot assigner per hdlc C clear to send/ready to receive (cts/rtr) hardware handshaking and auto-enable operation C collision detection for multidrop applications C transparency mode C address comparison on receive C flag or mark idle operation smartdma general- purpose dma (4) physical interface raw dce pcm serial communications peripherals tsa tsa tsa tsa muxing glueless interface to ram/rom dram controller am186 cpu chip selects (48) watchdog timer interrupt controller uart high-speed uart with autobaud usb synchronous hdlc hdlc hdlc hdlc (14) highway gci (iom-2) (17 ext. sources) pios serial interface (ssi) timers (3) system peripherals memory peripherals channels (8)
am186?cc communications controller data sheet 29 n four independent time slot assigners (tsas) provide flexible time slot allocation C allows isolation of time division multiplexed (tdm) time slot of choice from a variety of tdm carriers C up to 4096 sequential bits isolated C tdm bus can have up to 512 8-bit time slots C start bit and stop bit times identify isolated portion of tdm frame C 12-bit counters define the start/stop bit times as the number of bits after frame synchronization C entire frame down to 1 bit per frame can be isolated n 12 direct memory access (dma) channels C eight buffer descriptor ring smartdma channels for the four hdlc channels and, optionally, usb bulk and isochronous endpoints C four general-purpose dmas support the two integrated asynchronous serial ports and/or usb endpoints. two dma channels have external dma request inputs n high-speed asynchronous serial interface provides enhanced uart functions C capable of sustained operation at 460 kbaud C 7-, 8-, or 9-bit data transfers C fifos to support high-speed operation C dma support available C automatic baud rate detection that allows emulation of a hayes at-compatible modem C independent baud generator with clock input source programmable to use cpu or external clock input pin n asynchronous serial interface (uart) C 7-, 8-, or 9-bit data transfers C dma support available C independent baud generator with clock input source programmable to use cpu or external clock input pin n general circuit interface (gci) provides iom-2 terminal mode connection C glueless connection between the AM186CC microcontroller and gci-based isdn transceiver devices, such as the am79c30/am79c32 C four-pin gci connection C terminal mode operation C slave mode with pin reversal C telecom ic (tic) bus support for d channel arbitration and collision detection C support for one monitor and two command/ indicate channels C clock and frame sync conversion for pcm highway coder-decoders (codecs) n synchronous serial interface (ssi) provides half-duplex, bidirectional interface to high- speed peripherals C useful with many telecommunication interface peripherals such as codecs, line interface units, and tranceivers C selectable device-select polarity C selectable bit shift order on transmit and receive C glueless connection to amd subscriber line audio processing circuit (slac?) devices n clocking options offer high flexibility C separate crystal oscillator inputs for system and usb clock sources C cpu can run in 1x, 2x, or 4x mode C usb can run in 2x or 4x mode C usb can run from system clock if running at 48 mhz, allowing entire system to run from one 12-mhz or 24-mhz crystal am186 embedded cpu all members of the am186 family, including the AM186CC microcontroller, are compatible with the original industry-standard 186 parts, and build on the same core set of 186 registers, i/o space, address generation, instruction set, segments, data types, and addressing modes. memory organization memory is organized in sets of segments. each segment is a linear contiguous sequence of 64k (2 16 ) 8-bit bytes. memory is addressed using a two- component address consisting of a 16-bit segment value and a 16-bit offset. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, ss, or es). the physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see figure 2 on page 30). this allows for a 1-mbyte physical address size. all instructions that address operands in memory must specify the segment value and the 16-bit offset value. for speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see table 5 on page 30). i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions (in, ins and out, outs) address the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero- extended such that a15Ca8 are low.
30 am186?cc communications controller data sheet figure 2. two-component address example serial communications support the AM186CC microcontroller supports eight serial interfaces. this includes four hdlc channels, a usb peripheral controller, two uarts, and a synchronous serial interface. universal serial bus the AM186CC microcontroller includes a highly flexible integrated usb peripheral controller that lets designers implement a variety of microcontroller-based usb peripheral devices for telephony, audio, and other high-end applications. this integrated usb peripheral controller can provide a significant system-cost reduction compared to other platforms that require a separate usb controller. the AM186CC microcontroller can be used in self- powered usb peripherals that use the full-speed signalling rate of 12 mbit/s. the usb low-speed rate (1.5 mbit/s) is not supported. an integrated usb transceiver is provided to minimize system device count and cost, but an external transceiver can be used instead, if necessary. the usb controller does not support usb host or hub functions. however, the AM186CC microcontroller can be used to implement usb peripheral functions in a device that also contains separate usb hub circuitry. in addition, the AM186CC usb controller supports the following: n an unlimited number of device descriptors n a total of 6 endpoints: 1 control endpoint, 1 interrupt endpoint, and 4 data endpoints that can be configured as control, interrupt, bulk, or isochronous. the interrupt, bulk, and isochronous endpoints can be configured for the in or out direction. n two data endpoints have 16-byte fifos; two data endpoints have 64-byte fifos n fully integrated differential driver, which supports the usb interface directly n specialized hardware, which supports adaptive isochronous data streams and automatically synchronizes with hdlc data streams n general-purpose dma and smartdma channels table 5. segment register selection rules memory reference needed segment register used implicit segment selection rule instructions code (cs) instructions (including immediate data) local data data (ds) all data references stack stack (ss) all stack pushes and pops; any memory references that use the bp register external data (global) extra (es) all string instruction references that use the di register as an index 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memory offset 0 15 15 15 19 19 0 0 0 0
am186?cc communications controller data sheet 31 four hdlc channels and four tsas the AM186CC microcontroller provides four hdlc channels that support the hdlc, sdlc, lap-b, lap-d, ppp, and v.120 protocols. the hdlc channels can also be used in transparent mode to support v.110. each hdlc channel can connect to an external serial interface directly (nonmultiplexed mode), or can pass through a tsa (multiplexed mode). the flexible interface multiplexing arrangement allows each hdlc channel to have its own external raw dce or pcm highway interface, share the gci interface with up to two other channels, share a common pcm highway or other time tdm bus with three or more channels, or work in some combination. each hdlc channels independent tsa allows it to extract a subset of data from a tdm bus. the entire frame, or as little as 1 bit per frame, can be extracted. twelve-bit counters define the start/stop bit times as the number of bits after frame synchronization. the time slot can be an arbitrary number of bits up to 4096 bits. start bit and stop bit times identify the isolated portion of the tdm frame. support of less than eight bits per time slot, or bit slotting , allows isolation of from one to eight bits in a single time slot, providing a convenient way to work with d-channel data. each tdm bus can have up to 512 8-bit time slots. support of these features allows interoperation with pcm highway, e1, iom-2, t1, and other tdm buses. the hdlc channels have features that make the AM186CC microcontroller an attractive device for use where general hdlc capability is required. these features include cts/rtr hardware handshaking and auto-enable operation, collision detection for multidrop applications, transparency mode, address comparison on receive, flag or mark idle operation, two dedicated buffer descriptor ring smartdma channels per hdlc, transmit and receive fifos, and full-duplex data transfer. each tsa channel can support a burst data rate to/from the hdlc of up to 10 mbit/s in both raw dce and pcm highway modes, and up to 768 kbit/s in gci mode. total system data throughput is highly dependent on the amount of per-packet and per-byte cpu processing, the rate at which packets are being sent, and other cpu activity. when combined with the tsas, the hdlc channels can be used in a wide variety of applications such as isdn basic rate interface (bri) and primary rate interface (pri) b and d channels, pcm highway, x.25, frame relay, and other proprietary wide area network (wan) connections. general circuit interface the general circuit interface (gci) is an interface specification developed jointly by alcatel, italtel, gpt, and siemens. this specification defines an industry- standard serial bus for interconnecting telecommunications integrated circuits. the standard covers linecard, nt1, and terminal architectures for isdn applications. the AM186CC microcontroller supports the terminal version of gci. the AM186CC gci interface provides a glueless connection between the AM186CC microcontroller and gci/iom-2 based isdn transceiver devices, such as the amd am79c30 or am79c32. the AM186CC microcontroller gci interface provides a 4-pin connection to the transceiver device. the AM186CC microcontroller also allows conversion of the gci clock and frame synchronization into a format usable by pcm codecs, allowing pcm codecs to be used directly with gci/iom-2 transceivers. additional gci features include slave mode with pin reversal, terminal interchip communication (tic) bus support for d channel arbitration and collision detection, and support for one monitor and two command/indicate channels. eight smartdma ? channels the AM186CC microcontroller provides a total of 12 dma channels. eight of these channels are smartdma channels, which provide a method for transmission and reception of data across multiple memory buffers and a sophisticated buffer-chaining mechanism. these channels are always used in pairs: transmitter and receiver. the transmit channels can only transfer data from memory to a peripheral; the receive channels can only transfer data from a peripheral to memory. four of the channels (two pairs) are dedicated for use with two of the on-board hdlc channels. the remaining four smartdma channels (two pairs) can support either the third or fourth hdlc channel or usb endpoints a, b, c, or d. in addition to the eight smartdma channels, the AM186CC microcontroller provides four general- purpose dma channels. for more information about the four general-purpose dma channels, refer to four general-purpose dma channels on page 32. two asynchronous serial ports the AM186CC microcontroller has two asynchronous serial ports (a uart and a high-speed uart) that provide full-duplex, bidirectional data transfer at speeds of up to 115.2 kbit/s or up to 460 kbit/s, respectively. the high-speed uart has 16-byte transmit and 32-byte receive fifos, special-character matching, and automatic baud-rate detection, which is suitable for implementation of a hayes-compatible modem interface to a host pc. a lower speed uart is also available that is typically used for a low baud-rate system configuration port or debug port. each of these uarts can derive its baud rate from the system clock or from a separate baud-rate generator clock input. both uarts support 7-, 8-, or 9-bit data transfers;
32 am186?cc communications controller data sheet address bit generation and detection in 7- or 8-bit frames; one or two stop bits; even, odd, or not parity; break generation and detection; hardware flow control; and dma to and/or from the serial ports using the general-purpose dma channels. synchronous serial port the AM186CC microcontroller includes one ssi, which provides a half-duplex, bidirectional, communications interface between the AM186CC microcontroller and other system components. this interface is typically used by the AM186CC microcontroller to monitor the status of other system devices and/or to configure these devices under software control. in a communications application, these devices could be system components such as audio codecs, line interface units, and transceivers. the ssi supports data transfer speeds of up to 25 mbit/s with a 50-mhz system clock. the AM186CC ssi port operates as an interface master, with the other attached devices acting as slave devices. using this protocol, the AM186CC microcontroller sends a command byte to the attached device, and then follows that with either a read or write of a byte of data. the ssi port consists of three i/o pins: an enable (sden), a clock (sclk), and a bidirectional data pin (sdata). sden can be used directly as an enable for a single attached device. when more than one device requires control via the ssi, pios can be used to provide enable pins for those devices. the AM186CC ssi is, in general, software compatible with software written for the am186em ssi. (additional features have been added to the AM186CC ssi implementation.) in addition, the AM186CC microcontroller features the additional capability of selecting the polarity of the sclk and sden pins, as well as the shift order of bits on the sdata pin (least- significant-bit first versus most-significant-bit first). the AM186CC ssi port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to amd slac devices. system peripherals interrupt controller the AM186CC microcontroller features an interrupt controller, which arranges the 36 maskable interrupt requests by priority and presents them one at a time to the cpu. in addition to interrupts managed by the interrupt controller, the AM186CC microcontroller supports eight nonmaskable interruptsan external or internal nonmaskable interrupt (nmi), a trace interrupt, and software interrupts and exceptions. the AM186CC interrupt controller supports 36 maskable interrupt sources through the use of 15 channels. because of this, most channels support multiple interrupt sources. these channels are programmable to support the external interrupt pins and/ or various peripheral devices that can be configured to generate interrupts. the 36 maskable interrupt sources include 19 internal sources and 17 external sources. four general-purpose dma channels the AM186CC microcontroller provides a total of 12 dma channels. four of the channels are general purpose and can be used for data transfer between memory and i/o spaces (i.e., memory-to-i/o or i/o-to- memory) or within the same space (i.e., memory-to- memory or i/o-to-i/o). in addition, the AM186CC microcontroller supports data transfer between peripherals and memory or i/o. on-chip peripherals that support general-purpose dma are timer 2, the two asynchronous serial ports (uart and high-speed uart), and the usb controller. external peripherals support dma transfers through the external dma request pins. each general-purpose channel can accept synchronized dma requests from one of four sources: the dma request pins (drq1Cdrq0), timer 2, the uarts, or the usb controller. in addition to the four general-purpose channels, the AM186CC microcontroller provides eight smartdma channels. for more information about the eight smartdma channels, refer to eight smartdma? channels on page 31. 48 programmable i/o signals the AM186CC microcontroller provides 48 user- programmable input/output signals (pios). each of these signals shares a pin with at least one alternate function. if an application does not need the alternate function, the associated pio can be used by programming the pio registers. if a pin is enabled to function as a pio signal, the alternate function is disabled and does not affect the pin. a pio signal can be configured to operate as an input or output, with or without internal pullup or pulldown resistors (pullup or pulldown depends on the pin configuration and is not user-configurable), or as an open-drain output. additionally, eight pios can be configured as external interrupt sources. three programmable timers there are three 16-bit programmable timers in the AM186CC microcontroller. timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). these two timers can be used to count or time external events that drive the timer input pins. timers 0 and 1 can also be used to generate nonrepetitive or variable-duty-cycle waveforms on the timer output pins.
am186?cc communications controller data sheet 33 timer 2 is not connected to any external pins. it can be used by software to generate interrupts, or it can be polled for real-time coding and time-delay applications. timer 2 can also be used as a prescaler to timer 0 and timer 1, or as a dma request source. the source clock for timer 2 is one-fourth of the system clock frequency. the source clock for timers 0 and 1 can be configured to be one-fourth of the system clock, or they can be driven from their respective timer input pins. when driven from a timer input pin, the timer is counting the event of an input transition. the AM186CC microcontroller also provides a pulse width demodulation (pwd) option so that a toggling input signals low state and high state durations can be measured. hardware watchdog timer the AM186CC microcontroller provides a full-featured watchdog timer, which includes the ability to generate non-maskable interrupts (nmis), microcontroller resets, and system resets when the timeout value is reached. the timeout value is programmable and ranges from 2 10 to 2 26 processor clocks. the watchdog timer is used to regain control when a system has failed due to a software error or to failure of an external device to respond in the expected way. software errors can sometimes be resolved by recapturing control of the execution sequence via a watchdog-timer-generated nmi. when an external device fails to respond, or responds incorrectly, it may be necessary to reset the controller or the entire system, including external devices. the AM186CC watchdog timer provides the flexibility to support both nmi and reset generation. memory and peripheral interface system interfaces the AM186CC bus interface controls all accesses to the peripheral control block (pcb), memory-mapped and i/o-mapped external peripherals, and memory devices. internal peripherals are accessed by the bus interface through the pcb. the AM186CC bus interface features programmable bus sizing; individually selectable chip selects for the upper (ucs ) memory space, lower (lcs ) memory space, all non-ucs , non-lcs and i/o memory spaces; separate byte-write enables; and boot option from an 8- or 16-bit device. the integrated peripherals are controlled by 16-bit read/write registers. the peripheral registers are contained within an internal 1-kbyte control block. at reset, the base of the pcb is set to fc00h in i/o space. the registers are physically located in the peripheral devices they control, but they are addressed as a single 1-kbyte block. for registers, refer to the am186?cc/ ch/cu microcontrollers register set manual (order #21916). accesses to the pcb should be performed by direct processor actions. the use of dma to write or read from the pcb results in unpredictable behavior, except where explicit exception is made to support a peripheral function, such as the high-speed uart transmit and receive data registers. the 80c186 and 80c188 microcontrollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the AM186CC microcontroller continues to provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t 1 C t 4 ). during refresh cycles, the ad bus is driven during the t 1 phase and the values are unknown during the t 2 , t 3 , and t 4 phases. the value driven on the a bus is undefined during a refresh cycle. the nonmultiplexed address bus (a19Ca0) is valid one- half clkout cycle in advance of the address on the ad bus. when used with the modified ucs and lcs outputs and the byte write enable signals, the a19Ca0 bus provides a seamless interface to sram, dram, and flash/eprom memory systems. for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus on the AM186CC microcontroller during the normal address portion of the bus cycle for accesses to upper (ucs ) and/or lower (lcs ) address spaces. in this mode, the affected bus is placed in a high- impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the upper memory chip select (umcs) and lower memory chip select (lmcs) registers. when address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, thus decreasing power consumption, reducing processor switching noise, and preventing bus contention with memory devices and peripherals when operating at high clock rates. if the aden pin is asserted during processor reset, the value of the da bits in the umcs and lmcs registers is ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed address bus and providing support for existing emulation tools. for registers, refer to the am186?cc/ch/cu microcontrollers register set manual (order #21916). figure 3 on page 35 shows the affected signals during a normal read or write operation. the address and data are multiplexed onto the ad bus.
34 am186?cc communications controller data sheet figure 4 on page 36 shows a bus cycle when address bus disable is in effect, which causes the ad bus to operate in a nonmultiplexed data-only mode. the a bus has the address during a read or write operation. bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory- mapped and i/o-mapped peripherals and the peripheral control block. the AM186CC microcontroller provides an enhanced bus interface unit with the following features: n nonmultiplexed address bus n separate byte write enables for high and low bytes n output enable the standard 80c186/80c188 multiplexed address and data bus requires system interface logic and an ex- ternal address latch. on the AM186CC microcontroller, byte write enables and a nonmultiplexed address bus can reduce design costs by eliminating this external logic. nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one- half clkout cycle in advance of the address on the ad bus. when used in conjunction with the modified ucs and lcs outputs and the byte write enable signals, the a19Ca0 bus provides a seamless interface to external sram, and flash memory/eprom systems. byte write enables the AM186CC microcontroller provides the whb (write high byte) and wlb (write low byte) signals that act as byte write enables. whb is the logical or of bhe and wr . whb is low when both bhe and wr are low. wlb is the logical or of a0 and wr . wlb is low when a0 and wr are both low. the byte write enables are driven with the nonmultiplexed address bus as required for the write timing requirements of common srams. output enable the AM186CC microcontroller provides the rd (read) signal which acts as an output enable for memory or peripheral devices. the rd signal is low when a word or byte is read by the AM186CC microcontroller. dram support to support dram, the AM186CC microcontroller has a fully integrated dram controller that provides a glueless interface to 25C70-ns extended data out (edo) dram. (edo dram is sometimes called hyper-page mode dram.) up to two banks of 4-mbit (256 kbit x 16 bit) dram can be accessed. page mode dram, fast page mode dram, asymmetrical dram, and 8-bit wide dram are not supported. the AM186CC microcontroller includes a glueless dram interface providing zero-wait state operation at up to 50 mhz with 40-ns dram. this allows designs requiring larger amounts of memory to save system cost over sram designs by taking advantage of low dram memory costs. the dram interface uses various chip select pins to implement the ras/cas interface required by drams. the AM186CC dram controller drives the ras/cas interface appropriately during both normal memory accesses and during refresh. all signals required are generated by the AM186CC microcontroller and no external logic is required. the dram multiplexed address pins are connected to the AM186CC microcontrollers odd address pins, starting with a1 on the AM186CC microcontroller connecting to ma0 on the dram. the correct row and column addresses are generated on these odd address pins during a dram access. the ras pins are multiplexed with lcs and mcs3 , allowing a dram bank to be present in either high or low memory space. the mcs2 and mcs1 function as the upper and lower cas pins, respectively, and define which byte of data in a 16-bit dram is being accessed. the AM186CC microcontroller supports the most common dram refresh option, cas-before-ras. all refresh cycles contain three wait states to support the drams at various frequencies. the dram controller never performs a burst access. all accesses are single accesses to dram. if the pcs chip selects are decoded to be in the dram address range, pcs accesses take precedence over the dram. chip selects the AM186CC microcontroller provides six chip select outputs for use with memory devices and eight more for use with peripherals in either memory or i/o space. the six memory chip selects can be used to address three memory ranges. each peripheral chip select addresses a 256-byte block offset from a programmable base address. the AM186CC microcontroller can be programmed to sense a ready signal for each of the peripheral or memory chip select lines. a bit in each chip select control register determines whether the external ready signal is required or ignored. the chip selects can control the number of wait states inserted in the bus cycle. although most memory and peripheral devices can be accessed with three or less wait states, some slower devices cannot. this feature allows devices to use wait states to slow down the bus.
am186?cc communications controller data sheet 35 the chip select lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. general enhancements over the original 80c186 include bus mastering (three-state) support for all chip selects and activation only when the associated register is written, not when it is read. clock control the processor supports clock rates from 16 to 50 mhz using an integrated crystal oscillator and pll. commercial and industrial temperature ratings are available. separate crystal oscillator inputs are provided for the usb and cpu. flexibility is provided to run the entire device from a 12-, or 24-mhz crystal when the usb is in use. the cpu can run in 1x, 2x, or 4x mode; usb can run in 2x or 4x mode. figure 3. AM186CC controller address bus default operation clkout t 1 t 2 t 3 t 4 ad15Cad0 (read) data ad15Cad0 (write) lcs or ucs address data address address phase data phase a19Ca0 address mcsx , pcsx
36 am186?cc communications controller data sheet figure 4. AM186CC controlleraddress bus disable in effect clkout t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs or ucs ad15Cad8 (read) ad7Cad0 (read) address phase data data phase data a19Ca0 address
am186?cc communications controller data sheet 37 in-circuit emulator support because pins are an expensive resource, many play a dual role, and the programmer selects pio operation or an alternate function. however, a pin configured to be a pio may also be required for emulation support. therefore, it is important that before a design is committed to hardware, a user should contact potential emulator suppliers for a list of their emulators pin requirements. the following pio signals are multiplexed with alternate signals that may be used by emulators: pio8, pio15, pio33Cpio35. the AM186CC microcontroller was designed to minimize conflicts. in most cases, pin conflict is avoided. for example, if the ale signal is required for multiplex bus support, then it would not be programmed as pio33. if the multiplexed ad bus is not used, then ale can be programmed as a pio pin. if the multiplexed bus is not in use, then the emulator does not require the ale signal. however, an emulator is likely to always use the de-multiplexed address, regardless of how the ad bus is programmed. applications the AM186CC microcontroller, with its integrated hdlc, usb, and other communications features, provides a highly integrated, cost-effective solution for a wide range of telecommunications and networking applications. n isdn modems and terminal adapters: next- generation isdn equipment requires usb (or high- speed uart capability), in addition to three channels of hdlc. n low-end routers: isdn to ethernet-based per- sonal routers, often used for connections in small office/home office (soho) environments, require three channels of hdlc, as well as the high perfor- mance of a 16-bit controller. n linecard applications: typically, linecards used in central offices (cos), pabx equipment, and other telephony applications require one or two channels of hdlc. linecard manufacturers are moving to more lines per card for analog pots as a means of cost reduction. this, and digital linecards for sup- port of isdn, often require higher performance than existing 8-bit devices can offer. the AM186CC mi- crocontroller is an ideal solution for these applica- tions because it integrates much of the necessary glue logic while providing higher performance. n xdsl applications: todays xdsl applications, such as high-speed adsl modems, require data handling of 2 mbit/s or greater and can take advan- tage of the usb interface for easy connectivity to the pc. n digital corded phones: typical digital telephone applications use up to three channels of hdlc and may use usb for merged pc telephony applica- tions. n industrial control: embedded x86 processors have long been used in the industrial control mar- ket. these applications often require a robust, high- performance processor solution with one or two channels of hdlc. n usb peripheral devices: these devices will be- come more common as the pc market embraces the usb protocol. in addition to implementing com- munications device class systems such as an isdn terminal adapter, the usb controller makes the AM186CC microcontroller suitable for certain pc desktop applications such as a usb camera inter- face, ink-jet printers, and scanners. n general communications applications: the AM186CC microcontroller will also find a home in general embedded applications, because many de- vices will incorporate communications capability in the future. many designs are adding hdlc capabil- ity as a robust means of inter- and intra-system communications. the AM186CC microcontroller is especially attractive for 186 designs adding hdlc, usb, or both. block diagrams on the following pages show some typical AM186CC microcontroller designs: figure 5 on page 38 shows an isdn terminal adapter system application, figure 6 on page 38 shows an isdn to ethernet low-end router application, and figure 7 on page 39 shows a 32-channel linecard application. the isdn terminal adapter features an s/t or u interface and either a high-speed uart or usb connection for attaching the modem to the pc. the isdn-to-ethernet low-end router features an s/t or u interface, two pots lines, and a 10-mbit/s connection to the pc. the 32-channel linecard design demonstrates the AM186CC microcontrollers use in a linecard application where 32 incoming pots lines are aggregated onto a single e1 connection.
38 am186?cc communications controller data sheet i figure 5. isdn terminal adapter system application figure 6. isdn to ethernet low-end router system application
am186?cc communications controller data sheet 39 figure 7. 32-channel linecard system application
40 am186?cc communications controller data sheet clock generation and control the AM186CC controller clocks include the general system clock (clkout), usb clock, transmitter/ receiver clocks for each hdlc channel, and the baud rate generator clock for uart and high-speed uart. the ssi and the timers (timers 0, 1, and 2) derive their clocks from the system clock. features the AM186CC controller clocks include the following features and characteristics: n two independent crystal-controlled oscillators that use external fundamental mode crystals or oscillators to generate the system input clock and the usb input clock. n two independent internal plls, one of which generates a system clock (clkout) that is 1x, 2x, or 4x the system input clock, and one that generates the 48-mhz clock required for the usb from either a 48-, 24-, or 12-mhz input. n single clock source operation possible by sharing the clock source between the system and the usb. n each hdlc receives its clock inputs directly from the external communication clock pins (tclk _x and rclk_x) in all modes except in gci mode. in gci mode the external gci communication clocks (tclk_a and rclk_a) are first converted to an in- ternal clocking format (analogous to pcm highway) before presentation to the hdlc. the system clock must be at least the same frequency as any hdlc clock. C hdlc dce mode supports clocks up to 10 mhz. C hdlc pcm mode supports clocks up to 10 mhz. C hdlc gci mode supports a 1.536-mhz clock input. (system clock must be at least twice the gci clock.) n ssi clock (sclk) is derived from the system clock, divided by 2, 4, 8, 16, 32, 64, 128, or 256. n timers 0 and 1 can be configured to be driven by the timer input pins (tmrin1, tmrin0) or at one- fourth of the system clock. timer 2 is driven at one- fourth of the system clock. n uart clock can be derived from the internal system clock frequency or from the uart clock (uclk) input. see figure 8 on page 41 for a diagram of the basic clock generation and figure 9 on page 42 for suggested clock frequencies and modes. system clock the system pll generates frequencies from 16 to 50 mhz. the reference for the system pll can vary from 8 to 40 mhz, depending on the pll mode selected and the desired system frequency (see figure 9 on page 42). the system pll modes are chosen by the state of the {clksel1} and {clksel2} pins during reset. for these pinstrap settings see table 31, reset configuration pins (pinstraps), on page a-10. the system clock can be generated in one of two ways: n using the internal pll running at 1x, 2x, or 4x the reference clock. the reference clock can be generated from an external crystal using the integrated oscillator or an external oscillator input. n bypassing the internal pll. the external reference generated from either a crystal or an external oscillator input is used to generate the system clock. for more information about bypassing the internal pll, refer to pll bypass mode on page 43. usb clock the usb pll provides the 48-mhz clock that is required for usb full-speed operation. this clock is divided down to provide a 12-mhz clock that supports the full-speed usb rate (12 mbit/s). the low-speed rate of 1.5 mbit/s is not supported. the usb pll modes are chosen by the state of the {usbsel1} and {usbsel2} pins during reset. for these pinstrap settings, refer to table 31, reset configuration pins (pinstraps), on page a-10. the usb clock can be generated in one of two ways: n using the system clock. in this mode, the system pll is restricted to 48-mhz operation only. note: when using the system clock for the usb clock source, the designer must externally pull down the usbx1 input. n using its own internal 48-mhz pll. this pll can run in 2x or 4x mode and requires a 12- or 24-mhz reference that can be generated by either the integrated crystal-controlled oscillator or an external oscillator input. note: the system clock must be a minimum of 24 mhz when using the usb peripheral controller and its internal 48-mhz pll. the usb specification requires a frequency tolerance of less than 2500 ppm, which must be met whether using an external clock source, a crystal on usbx1C usbx2, or clock sharing by system and usb. when using a crystal, some frequency tolerance margin must be allowed to account for the differences in external loading capacitances, etc. the usual rule of thumb is to specify a crystal with a frequency tolerance of one half the required frequency tolerance.
am186?cc communications controller data sheet 41 clock sharing by system and usb the system and usb clocks can be generated from a single source in one of two ways: n the system can run at 48 mhz by using the system clock for the usb clock. note: when using the system clock for the usb clock source, the designer must externally pull down the usbx1 input. n the system can be run at 24 mhz by sharing an external clock reference (x1) with the usb (usbx1). a 12-mhz source can be used with the system pll in 2x mode and the usb pll in 4x mode, or a 24-mhz source can be used with the system in 1x mode and the usb in 2x mode. figure 8. system and usb clock generation {clksel2}C{clksel1} clkout pll bypass mode 48-mhz usb clock {usbsel2}C{usbsel1} 1x 2x 4x 2x 4x x1 x2 AM186CC controller pll pll usbx1 usbx2 system clock
42 am186?cc communications controller data sheet figure 9. suggested system clock frequencies, clock modes, and crystal frequencies crystal-driven clock source the internal oscillator circuit is designed to function with an external parallel-resonant fundamental mode crystal. the crystal frequency can vary from 8 to 40 mhz, depending on the pll mode selected and de- sired system frequency. when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause variance in the oscillation frequency from the desired specified value (resonance). the load capacitance and the loading of the feedback network have the following relationship: where c s is the stray capacitance of the circuit. table 6 shows crystal parameter values. figure 10 shows the system clocks using an external crystal and the integrated oscillator. the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. figure 10. external interface to support clocks fundamental mode crystal 8-mhz to 25-mhz xtal or clock 4x mode 2x mode 1x mode 32 mhz system operating frequency 1 the crystal oscillator is not guaranteed above 40 mhz. 16 mhz 20 mhz 30 mhz 40 mhz 50 mhz 0-mhz to 24-mhz xtal or clock 0 mhz 24 mhz pll bypass mode 8-mhz to 12.5-mhz xtal or clock 1x mode 2x mode 4x mode 16-mhz to 40-mhz xtal or clock 1 pll bypass mode (c 1 c 2 ) c l = ( c 1 + c 2 ) + c s table 6. crystal parameters parameter min. value max. value units frequency 8 40 mhz esr 8C24 mhz 20 90 ohms 24C50 mhz 20 60 ohms load capacitance 10 pf c2 c1 xtal x1/usbx1 x2/usbx2
am186?cc communications controller data sheet 43 external clock source the internal oscillator also can be driven by an external clock source. the external clock source should be connected to the input of the inverting amplifier (x1 or usbx1) with the output (x2 or usbx2) left unconnected. figure 11 shows the system clocks using an external clock source (oscillator bypass). note: x1, x2, usbx1, and usbx2 are not 5-v toler- ant and have a maximum input equal to v cc . figure 11. external interface to support clocks external clock source static operation the AM186CC controller is a fully static design and can be placed in static mode by stopping the input clock. pll bypass mode must be used with an external clock source. for pll bypass mode, refer to the pll bypass mode discussion below. note: it is the responsibility of the system designer to ensure that no short clock phases are generated when starting or stopping the clock. pll bypass mode the am 186cc microcontroller provides a pll bypass mode that allows the x1 input frequency to be anywhere from 0 to 24 mhz. when the microcontroller is in pll bypass mode, the clkout frequency equals the x1 input frequency. this mode must be used with an external clock source. for pll bypass mode enabling, refe r to table 31, reset configuration pins (pinstraps), on page a-10. when changing frequency in pll bypass mode, the x1 input must not have any short or runt pulses. at 24 mhz, the nominal high/low time is 21 ns. the actual high times and low times must not fall below 16 ns. these values allow a 60%/40% duty cycle at x1. in the AM186CC microcontroller, the system clock must be at the same or a greater frequency than the hdlc clock and uclk (if using uclk). therefore, if reducing the system clock frequency, disable these interfaces or run them at a lower frequency. the usb pll and usbx1 determine the usb clock. usb requires the system clock to be 24 mhz or greater. therefore, disable the usb peripheral controller before slowing the system clock to less than 24 mhz. if usb is not used, the usbx1 can be pulled down. uart baud clock the uarts (low- and high-speed) have two possible clock sources: the system clock or the uclk input pin. if uclk is used for the uart clock, the system clock must be at least the same frequency as uclk. the clock configurations are shown graphically in figure 12. the baud clock is generated by dividing the clock source by the value of baud rate divisor register. the serial port logic can select its baud rate clock from either an external pin (uclk) or from the system clock. the system or uclk clock is selected independent of any other settings. the formula for determining the baud rate divisor register value is: bauddiv = (clock frequency/(16 ? baud rate)) note: uclk cannot be clocked at a frequency higher than the system cock frequency. figure 12. uart and high-speed uart clocks external clock x1/usbx1 x2/usbx2 nc baud divisor system clock uclk uart/high-speed uart oversampling clock oversample baud clock divide for autobaud clock clock select (high-speed uart only)
44 am186?cc communications controller data sheet power supply operation cmos dynamic power consumption is proportional to the square of the operating voltage multiplied by capacitance and operating frequency. static system operation can reduce power consumption by enabling the system designer to reduce operating frequency when possible. however, operating voltage is always the dominant factor in power consumption. by reducing the operating voltage from 5 v to 3.3 v for any device, the power consumed is reduced by 56%. reduction of system logic operating voltage dramatical- ly reduces overall system power consumption. addition- al power savings can be realized as low-voltage mass storage and peripheral devices become available. two basic strategies exist in designing systems containing the AM186CC controller. the first strategy is to design a homogenous system in which all logic components operate at 3.3 v. this provides the lowest overall power consumption. however, system designers may need to include devices for which 3.3-v versions are not available. in the second strategy, the system designer must then design a mixed 5-v/3.3-v system. this compromise enables the system designer to minimize the system logic power consumption while still including the functionality of the 5-v features. the choice of a mixed voltage system design also involves balancing design complexity with the need for the additional features. power supply connections connect all v cc pins together to the 3.3-v power supply and all ground pins to a common system ground. input/output circuitry to accommodate current 5-v systems, the AM186CC controller has 5-v tolerant i/o drivers. the drivers produce ttl-compatible drive output (minimum 2.4-v logic high) and receive ttl and cmos levels (up to v cc + 2.6 v). the following are some design issues that should be considered with mixed 3.3-v/5-v designs: n during power-up, if the 3.3-v supply has a significant delay in achieving stable operation relative to 5-v supply, then the 5-v circuitry in the system may start driving the processors inputs above the maximum levels (v cc + 2.6 v). the system design should ensure that the 5-v supply does not exceed 2.6 v above the 3.3-v supply during a power-on sequence. n preferably, all inputs are driven by sources that can be three-stated during a system reset condition. the system reset condition should persist until stable v cc conditions are met. this should help ensure that the maximum input levels are not exceeded during power-up conditions. n preferably, all pullup resistors are tied to the 3.3-v supply, which ensures that inputs requiring pullups are not over stressed during power-up. pio supply current limit each programmable i/o output is able to sink or source a sustained 16-ma drive current. however, only 40 ma of sustained pio current is allowed for each supply pin (v cc ), and only 60 ma is allowed for each ground pin (v ss ). to calculate the pio current for each supply or ground pin, sum the applicable current (source or sink) of all pio pins on either side of the pin (to the adjacent corresponding pins), and divide the sum by two. the resulting value should not exceed 40 ma for v cc or 60 ma for v ss . exclude the following pins from this calculation: 72 (v ss _a), 82 (v ss _usb), 77 (v cc _a), and 79 (v cc _usb). for example, to calculate the pio current for pin 83 (v ss ), total the sustained sinking current for all pio pins between pin 71 (v ss ) and pin 100 (v ss ), and divide the sum by two.
am186?cc communications controller data sheet 45 driver characteri sticsuniversal serial bus each usbd+ and usbdC pin connects through a series resistor directly to the usb. the series resistor value should be selected to achieve a total driver impedance between 29 and 44 ohms, as required by the usb version 1.0 specification. a 36- w 1% series resistor is recommended for each pin. characteristics of these two pins are defined in the usb version 1.0 specification. consult this specification for details about overall usb system design. (at the time of this writing, the current usb specification and related information can be obtained on the web at www.usb.org .) the AM186CC controller is guaranteed to meet all usb specifications. required analog transceivers are integrated into the AM186CC controller. absolute maximum ratings 1 notes: 1. stresses above those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. parameter symbol minimum maximum unit temperature under bias: commercial t c 2 2. t c = case temperature. 0100 c industrial t a 3 3. t a = ambient temperature. C40 +85 c storage temperature C65 +150 c voltage on 5-v-tolerant pins 4 with respect to ground 4. 5 v-tolerant pins are indicated in table 35, pin list summary, on page a-12. C0.5 v cc + 2.6 v voltage on other pins with respect to ground C0.5 v cc + 0.5 v sustained pio current on any supply (v cc ) pin 5 5. see pio supply current limit on page 44. 40ma sustained pio current on any ground (v ss ) pin 5 60ma operating ranges 1 notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. parameter symbol minimum maximum unit commercial t c 2 2. t c = case temperature. 0100c industrial t a 3 3. t a = ambient temperature. C40 + 85 c supply voltage with respect to ground v cc 3.0 3.6 v
46 am186?cc communications controller data sheet dc characteristics over commercial and industrial operating ranges 1 notes: 1. current out of pin is stated as a negative value. symbol parameter preliminary unit minimum maximum v oh output high voltage (i oh = C2.4 ma) 2.4 v v oh output high voltage (i oh = C0.1 ma) 2 2. characterized but not tested. v cc - 0.2 v v ol output low voltage (i ol = 4.0 ma) 0.45 v v ih5 5-v tolerant input high voltage 2.0 v cc + 2.6 v v ih input high voltage, except 5-v tolerant 2.0 v cc +0.3 v v il input low voltage C0.3 0.8 v i li input leakage current (0.1 v ? v out ? v cc ) (all pins except those with internal pullup/pulldown resistors) 10 m a i lo output leakage current 3 (0.1 v ? v out ? v cc ) 3. this parameter is for three-state outputs where v out is driven on the three-state output. 15 m a p cc power consumption 1.2 w capacitance symbol parameter preliminary unit minimum maximum c in input capacitance 15 pf c clk clock capacitance 15 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf
am186?cc communications controller data sheet 47 maximum load derating all maximum delay numbers should be increased by 0.035 ns for every pf of load (up to a maximum of 150 pf) over the maximum load specified in table 35, pin list summary, on page a-12. power supply current for the following typical system specification shown in figure 13, i cc has been measured at 6 ma per mhz of system clock. the typical system is measured while the system is executing code in a typical application with nominal voltage and maximum case temperature. actual power supply current is dependent on system design and may be greater or less than the typical i cc figure presented here. typical current in figure 13 is given by: i cc = 6 ma ? freq(mhz) please note that dynamic i cc measurements are de- pendent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the out- puts. for these i cc measurements, the devices were set to the following modes: n no dc loads on the output buffers n output capacitive load set to 30 pf n ad bus set to data only n pios are disabled n timer, serial port, refresh, and dma are enabled table 7 shows the values that are used to calculate the typical power consumption value for the AM186CC controller. figure 13. typical i cc versus frequency table 7. typical power consumption calculation mhz ? i cc ? volts / 1000 = p typical power in watts mhz typical i cc volts 25 6 3.3 0.495 40 6 3.3 0.792 50 6 3.3 0.99 clock frequency (mhz) i cc (ma) 0 40 80 120 160 200 240 280 10 20 30 40 50 320
48 am186?cc communications controller data sheet thermal characteristics pqfp package the AM186CC controller is specified for operation with case temperature ranges from 0 ? c to +100 ? c for 3.3 v 0.3 v (commercial). case temperature is measured at the top center of the package as shown in figure 14. the various temperatures and thermal resistances can be determined using the equations in figure 15 with information given in table 8. the total thermal resistance is q ja ; q ja is the sum of q jc , the internal thermal resistance of the assembly, and q ca , the case to ambient thermal resistance. the variable p is power in watts. power supply current (i cc) is in ma per mhz of clock frequency. figure 14. thermal resistance( ? c/watt) figure 15. thermal characteristics equations q ja q ca q jc q ja = q jc + q ca t c table 8. thermal characteristics ( ? c/watt) package/board airflow (linear feet per minute) q jc q ca q ja pqfp/2-layer 0 fpm 7 38 45 200 fpm 7 32 39 400 fpm 7 28 35 600 fpm 7 26 33 pqfp/4-layer to 6-layer 0 fpm 5 18 23 200 fpm 5 16 21 400 fpm 5 14 19 600 fpm 5 12 17 q ja = q jc + q ca p = i cc ? freq (mhz) ? v cc t j = t c + (p ? q jc ) t j = t a + (p ? q ja ) t c = t j C (p ? q jc ) t c = t a + (p ? q ca ) t a = t j C (p ? q ja ) t a = t c C (p ? q ca )
am186?cc communications controller data sheet 49 commercial and industrial switching characteristics and waveforms in the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. these periods are referred to as time states. a typical bus cycle is composed of four consecutive time states: t 1 , t 2 , t 3 , and t 4 . wait states, which represent multiple t 3 states, are referred to as t w states. when no bus cycle is pending, an idle (t i ) state occurs. in the switching parameter descriptions, the multiplexed address is referred to as the ad address bus; the demultiplexed address is referred to as the a address bus. figure 16 defines symbols used in the switching waveform diagrams. table 9 on page 50 contains an alphabetical listing of the switching parameter symbols, and table 10 on page 54 contains a numerical listing of the switching parameter symbols. figure 16. key to switching waveforms must be steady will be steady will be changing from h to l or from h to three-state will be changing from l to h or from l to three- state waveform input output may change from h to l or from h to three- state may change from l to h or from l to three- state
50 am186?cc communications controller data sheet table 9. alphabetical key to switching parameter symbols parameter symbol no. description t arych 49 ardy resolution transition setup time t arychl 51 ardy inactive holding time t aryhdsh 95 1 ardy high to ds high t aryhdv 89 1 ardy assert to data valid t arylcl 52 ardy setup time t aryldsh 96 1 ardy low to ds high t avbl 87 a address valid to whb , wlb low t avch 14 ad address valid to clock high t avll 12 ad address valid to ale low t avrl 66 a address valid to rd low t avwl 65 a address valid to wr low t azrl 24 ad address float to rd active t ch1ch2 45 clkout rise time t chav 68 clkout high to a address valid t chcas 404 change in cas delay t chck 38 x1 high time t chcl 44 clkout high time t chcsv 67 clkout high to lcs /ucs valid t chcsx 18 mcs /pcs inactive delay t chctv 22 control active delay 2 t chcv 64 command lines valid delay (after float) t chcz 63 command lines float delay t chdx 8 status hold time t chlh 9 ale active delay t chll 11 ale inactive delay t chq0sv 55 queue status 0 output delay t chq1sv 56 queue status 1 output delay t chras 403 change in ras delay t chrfd 79 1 clkout high to rfsh valid t chsv 3 status active delay t cico 69 x1 to clkout skew t ckhl 39 x1 fall time t ckin 36 x1 period t cklh 40 x1 rise time t cl2cl1 46 clkout fall time t clarx 50 ardy active hold time t clav 5 ad address and bhe valid delay t clax 6 address hold t claz 15 ad address float delay t clch 43 clkout low time t clck 37 x1 low time t clcl 42 clkout period t clclx 80 1 lcs inactive delay
am186?cc communications controller data sheet 51 t clcsl 81 1 lcs active delay t clcsv 16 mcs /pcs active delay t cldox 30 data hold time t cldv 7 data valid delay t cldx 2 data in hold t clhav 62 hlda valid delay t clrf 82 1 clkout high to rfsh invalid t clrh 27 rd inactive delay t clrl 25 rd active delay t clsh 4 status and bhe inactive delay t clsry 48 srdy transition hold time t cltmv 54 timer output delay t colv 402 column address valid delay t csharyl 88 1 chip select to ardy low t cvctv 20 control active delay 1 t cvctx 31 control inactive delay t cvdex 21 den /ds inactive delay t cxcsx 17 mcs /pcs hold from command inactive t dshdir 92 1 ds high to data invalid read t dshdiw 98 1 ds high to data invalidwrite t dshdx 93 1 ds high to data bus turn-off time t dshlh 41 ds inactive to ale inactive t dsldd 90 1 ds low to data driven t dsldv 91 1 ds low to data valid t dvcl 1 data in setup t dvdsl 97 1 data valid to ds low t dxdl 19 den /ds inactive to dt/r low t hvcl 58 hold setup t invch 53 peripheral setup time t lcrf 86 1 lcs inactive to rfsh active delay t lhav 23 ale high to address valid t lhll 10 ale width t llax 13 ad address hold from ale inactive t lrll 84 1 lcs precharge pulse width t resin 57 res setup time t rfcy 85 1 rfsh cycle time t rhav 29 rd inactive to ad address active t rhdx 59 rd high to data hold on ad bus t rhdz 94 1 rd high to data bus turn-off time t rhlh 28 rd inactive to ale high t rlrh 26 rd pulse width t srycl 47 srdy transition setup time table 9. alphabetical key to switching parameter symbols (continued) parameter symbol no. description
52 am186?cc communications controller data sheet t whdex 35 wr inactive to den inactive t whdx 34 data hold after wr t whlh 33 wr inactive to ale high t wlwh 32 wr pulse width usb timing (clocks) t uchck 3 usbx1 high time t uckhl 4 usbx1 fall time t uckin 1 usbx1 period t ucklh 5 usbx1 rise time t uclck 2 usbx1 low time usb timing (data/jitter) t f 2fall time t jr1 3 consecutive transition jitter t jr2 4 paired transition jitter t r 1rise time dce t tclkh 2 dce clock high t tclkhd 6 dce clock hold t tclkl 3 dce clock low t tclko 4 dce clock to output delay t tclkper 1 dce clock period t tclkr 7 dce clock rise/fall t tclksu 5 dce clock setup pcm (slave) t clkp 1 pcm clock period t dcd 8 delay time from clk high to txd valid t dclt 13 delay from clk low of last bit to tsc invalid t dct 11 delay to tsc valid from clk t dft 12 delay to tsc valid from fsc t dtw 17 delay from last bit clk low to txd weak drive t dzf 5 delay time to valid txd from clk t dzf 6 delay time to valid txd from fsc t hcd 10 hold time from clk low to rxd invalid t hcf 4 hold time from clk low to fsc valid t hfi 14 hold time from clk low to fsc invalid t sudc 9 setup time from rxd valid to clk t sufc 7 setup time for fsc high to clk low t synss 15 time between successive synchronization pulses t wh 2 pcm clock high t wl 3 pcm clock low t wsyn 16 fsc width invalid t dtz 18 delay from last bit clk (plus one) high to txd disable table 9. alphabetical key to switching parameter symbols (continued) parameter symbol no. description
am186?cc communications controller data sheet 53 pcm (master) t dcfh 1 delay time from clk high to fsc high t dcfl 2 delay time from clk high to fsc low gci t dhc 9 data hold/clock t dsc 7 data delay/clock t dsf 8 data delay/fsc t fd 5frame delay/clock t fh 4 frame hold/clock t hd 11 data hold t sd 10 data setup t sf 3 frame setup t wfh 6 frame width high t wh 1 pulse width high t wl 2 pulse width low ssi t clev 1 clkout low to sden valid t clsl 2 clkout low to sclk low t dvsh 3 data valid to sclk high t shdx 4 sclk high to data invalid t sldv 5 sclk low to data valid notes: 1. specification defined but not in use at this time. table 9. alphabetical key to switching parameter symbols (continued) parameter symbol no. description
54 am186?cc communications controller data sheet table 10. numerical key to switching parameter symbols no. parameter symbol description 1t dvcl data in setup 2t cldx data in hold 3t chsv status active delay 4t clsh status and bhe inactive delay 5t clav ad address and bhe valid delay 6t clax address hold 7t cldv data valid delay 8t chdx status hold time 9t chlh ale active delay 10 t lhll ale width 11 t chll ale inactive delay 12 t avll ad address valid to ale low 13 t llax ad address hold from ale inactive 14 t avch ad address valid to clock high 15 t claz ad address float delay 16 t clcsv mcs /pcs active delay 17 t cxcsx mcs /pcs hold from command inactive 18 t chcsx mcs /pcs inactive delay 19 t dxdl den /ds inactive to dt/r low 20 t cvctv control active delay 1 21 t cvdex den /ds inactive delay 22 t chctv control active delay 2 23 t lhav ale high to address valid 24 t azrl ad address float to rd active 25 t clrl rd active delay 26 t rlrh rd pulse width 27 t clrh rd inactive delay 28 t rhlh rd inactive to ale high 29 t rhav rd inactive to ad address active 30 t cldox data hold time 31 t cvctx control inactive delay 32 t wlwh wr pulse width 33 t whlh wr inactive to ale high 34 t whdx data hold after wr 35 t whdex wr inactive to den inactive 36 t ckin x1 period 37 t clck x1 low time 38 t chck x1 high time 39 t ckhl x1 fall time 40 t cklh x1 rise time 41 t dshlh ds inactive to ale inactive 42 t clcl clkout period 43 t clch clkout low time
am186?cc communications controller data sheet 55 44 t chcl clkout high time 45 t ch1ch2 clkout rise time 46 t cl2cl1 clkout fall time 47 t srycl srdy transition setup time 48 t clsry srdy transition hold time 49 t arych ardy resolution transition setup time 50 t clarx ardy active hold time 51 t arychl ardy inactive holding time 52 t arylcl ardy setup time 53 t invch peripheral setup time 54 t invcl drq setup time 54 t cltmv timer output delay 56 t chqsv queue status output delay 57 t resin res setup time 58 t hvcl hold setup 59 t rhdx rd high to data hold on ad bus 62 t clhav hlda valid delay 63 t chcz command lines float delay 64 t chcv command lines valid delay (after float) 65 t avwl a address valid to wr low 66 t avrl a address valid to rd low 67 t chcsv clkout high to lcs /ucs valid 68 t chav clkout high to a address valid 69 t cico x1 to clkout skew 79 t chrfd clkout high to rfsh valid 80 1 t clclx lcs inactive delay 81 1 t clcsl lcs active delay 82 1 t clrf clkout high to rfsh invalid 84 1 t lrll lcs precharge pulse width 85 1 t rfcy rfsh cycle time 86 1 t lcrf lcs inactive to rfsh active delay 87 1 t avbl a address valid to whb , wlb low 88 1 t csharyl chip select to ardy low 89 1 t aryhdv ardy assert to data valid 90 1 t dsldd ds low to data driven 91 1 t dsldv ds low to data valid 92 1 t dshdir ds high to data invalid read 93 1 t dshdx ds high to data bus turn-off time 94 1 t rhdz rd high to data bus turn-off time 95 1 t aryhdsh ardy high to ds high 96 1 t aryldsh ardy low to ds high 97 1 t dvdsl data valid to ds low table 10. numerical key to switching parameter symbols (continued) no. parameter symbol description
56 am186?cc communications controller data sheet 98 1 t dshdiw ds high to data invalid write 402 t colv column address valid delay 403 t chras change in ras delay 404 t chcas change in cas delay usb timing (clocks) 1t uckin usbx1 period 2t uclck usbx1 low time 3t uchck usbx1 high time 4t uckhl usbx1 fall time 5t ucklh usbx1 rise time usb timing (data/jitter) 1t r rise time 2t f fall time 3t jr1 consecutive transition jitter 4t jr2 paired transition jitter dce 1t tclkper dce clock period 2t tclkh dce clock high 3t tclkl dce clock low 4t tclko dce clock to output delay 5t tclksu dce clock setup 6t tclkhd dce clock hold 7t tclkr dce clock rise/fall pcm (slave) 1t clkp pcm clock period 2t wh pcm clock high 3t wl pcm clock low 4t hcf hold time from clk low to fsc valid 5t dzf delay time to valid txd from clk 6t dzf delay time to valid txd from fsc 7t sufc setup time for fsc high to clk low 8t dcd delay time from clk high to txd valid 9t sudc setup time from rxd valid to clk 10 t hcd hold time from clk low to rxd invalid 11 t dct delay to tsc valid from clk 12 t dft delay to tsc valid from fsc 13 t dclt delay from clk low of last bit to tsc invalid 14 t hfi hold time from clk low to fsc invalid 15 t synss time between successive synchronization pulses 16 t wsyn fsc width invalid 17 t dtw delay from last bit clk low to txd weak drive 18 t dtz delay from last bit clk (plus one) high to txd disable table 10. numerical key to switching parameter symbols (continued) no. parameter symbol description
am186?cc communications controller data sheet 57 pcm (master) 1t dcfh delay time from clk high to fsc high 2t dcfl delay time from clk high to fsc low gci 1t wh pulse width high 2t wl pulse width low 3t sf frame setup 4t fh frame hold/clock 5t fd frame delay/clock 6t wfh frame width high 7t dsc data delay/clock 8t dsf data delay/fsc 9t dhc data hold/clock 10 t sd data setup 11 t hd data hold ssi 1t clev clkout low to sden valid 2t clsl clkout low to sclk low 3t dvsh data valid to sclk high 4t shdx sclk high to data invalid 5t sldv sclk low to data valid notes: 1. specification defined but not in use at this time. table 10. numerical key to switching parameter symbols (continued) no. parameter symbol description
58 am186?cc communications controller data sheet switching characteristics over commercial and industrial operating ranges in this section the following timings and timing waveforms are shown: n read (page 58) n write (page 61) n software halt (page 64) n peripheral (page 65) n reset (page 66) n external ready (page 68) n bus hold (page 69) n system clocks (page 71) n usb clocks (page 72) n gci bus (page 73) n pcm highway (slave) (page 74) n pcm highway (master) (page 76) n dce interface (page 77) n usb (page 78) n ssi (page 79) n dram (page 80) table 11. read cycle timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max general timing requirements 1t dvcl data in setup 10 55ns 2t cldx data in hold 2 322ns general timing responses 3t chsv status active delay 0 20 0 12 0 10 ns 4t clsh status and bhe inactive delay 020012010ns 5t clav ad address and bhe valid delay 020012010ns 6t clax address hold 0 0 0 ns 8t chdx status hold time 0 0 0 ns 9t chlh ale active delay 20 12 10 ns 10 t lhll ale width t clcl C10=30 t clcl C5=20 t clcl C5=15 ns 11 t chll ale inactive delay 20 12 10 ns 12 t avll ad address valid to ale low 3 0.5 ? t clch 0.5 ? t clch 0.5 ? t clch ns 13 t llax ad address hold from ale inactive 3 t chcl t chcl t chcl ns 14 t avch ad address valid to clock high 000ns 15 t claz ad address float delay t clax =0 20 t clax =0 12 t clax =0 10 ns 16 t clcsv mcs /pcs active delay 020012010ns 17 t cxcsx mcs /pcs hold from command inactive t clch t clch t clch ns 18 t chcsx mcs /pcs inactive delay 020012010ns 19 t dxdl den /ds inactive to dt/r low 3, 4 C1 C1 C1 ns 20 t cvctv control active delay 1 020012010ns
am186?cc communications controller data sheet 59 21 t cevdx den /ds inactive delay 4 020012010ns 22 t chctv control active delay 2 020012010ns 23 t lhav ale high to address valid 15 7.5 5 ns read cycle timing responses 24 t azrl ad address float to rd active 000ns 25 t clrl rd active delay 020010010ns 26 t rlrh rd pulse width 2t clcl C15=65 2t clcl C10=40 2t clcl C10=30 ns 27 t clrh rd inactive delay020012010ns 28 t rhlh rd inactive to ale high 3 t clch C3 t clch C2 t clch C2 ns 29 t rhav rd inactive to ad address active 3 t clcl C10=30 t clcl C5=20 t clcl C5=15 ns 59 t rhdx rd high to data hold on ad bus 2 320ns 66 t avrl a address valid to rd low 1.5t clcl C15=45 1.5t clcl C10= 27.5 1.5t clcl C10=20 ns 67 t chcsv clkout high to lcs /ucs valid 020010010ns 68 t chav clkout high to a address valid 020010010ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown i n table 35, pin list summary, on page a-12. 2. if either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly. 3. testing is performed with equal loading on referenced pins. 4. the timing of this signal is the same for a read cycle, whether it is configured to be den or ds . table 11. read cycle timing 1 (continued) parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max
60 am186?cc communications controller data sheet figure 17. read cycle waveforms t4 t1 t2 t3 t4 1 2 14 12 13 24 59 29 10 10 28 26 26 17 19 68 3 8 5 15 9 11 25 27 67 16 18 20 21 22 22 3 4 addr. data clkout a19 Ca0 s6 1 ad15Cad0 ale rd bhe lcs , ucs mcs 3 Cmcs0 , den , ds dt/r s2 Cs0 6 23 4 5 tw 66 notes: 1. s6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t chsv )) is met. pcs 7 Cpcs0
am186?cc communications controller data sheet 61 table 12. write cycle timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max general timing responses 3t chsv status active delay 0 20 0 12 0 10 ns 4t clsh status and bhe inactive delay 020012010ns 5t clav ad address and bhe valid delay 020012010ns 6t clax address hold 0 00ns 7t cldv data valid delay 0 20 0 12 0 10 ns 8t chdx status hold time 0 0 0 ns 9t chlh ale active delay 20 12 10 ns 10 t lhll ale width t clcl C 10 = 30 t clcl C 5 = 20 t clcl C 5 = 15 ns 11 t chll ale inactive delay 20 12 10 ns 12 t avll ad address valid to ale low 2 0.5 ? t clch 0.5 ? t clch 0.5 ? t clch ns 13 t llax ad address hold from ale inactive t chcl t chcl t chcl ns 14 t avch ad address valid to clock high 000ns 16 t clcsv mcs /pcs active delay 020012010ns 17 t cxcsx mcs /pcs hold from command inactive t clch t clch t clch ns 18 t chcsx mcs /pcs inactive delay 020012010ns 19 t dxdl den inactive to dt/r 2, 3 C1 C1 C1 ns 20 t cvctv control active delay 1 3,4 020012010ns 21 t cvdex ds inactive delay 3,4 020012010ns 23 t lhav ale high to address valid 15 7.5 5 ns
62 am186?cc communications controller data sheet write cycle timing responses 30 t cldox data hold time 0 00ns 31 t cvctx control inactive delay 3,4 020012010ns 32 t wlwh wr pulse width 2t clcl C 10 = 70 2t clcl C 10 = 40 2t clcl C 10 = 30 ns 33 t whlh wr inactive to ale high 2 t clch C 2 t clch C 2 t clch C 2 ns 34 t whdx hold data after wr 2 t clcl C 10 = 30 t clcl C 10 = 15 t clcl C 10 = 10 ns 35 t whdex wr inactive to den inactive 2,3 t clch C 3 t clch t clch ns 65 t avwl a address valid to wr low t clcl + t chcl C3 t clcl + t chcl C 1.25 t clcl + t chcl C 1.25 ns 67 t chcsv clkout high to lcs /ucs valid 020010010ns 68 t chav clkout high to a address valid 020010010ns 87 t avbl a address valid to whb , wlb low t chcl C 3 20 t chcl C 1.25 12 t chcl C 1.25 10 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. testing is performed with equal loading on referenced pins. 3. the timing of this signal is different during a write cycle depending on whether it is configured to be den or ds . 4. this parameter applies to the den , ds , wr , whb , and wlb signals. table 12. write cycle timing 1 (continued) parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max
am186?cc communications controller data sheet 63 figure 18. write cycle waveforms t4 t1 t2 t3 t4 14 87 12 13 34 10 33 32 35 17 19 68 3 8 5 7 30 9 11 20 31 20 31 67 16 18 31 3 4 addr. data clkout a19Ca0 s6 1 ad15ad0 ale wr whb , wlb bhe lcs , ucs mc s3 Cmcs0 , den dt/r s2 Cs0 23 6 tw 5 20 20 31 20 21 ds 65 4 pcs 7 Cpcs0 notes: 1. s6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t chsv )) is met.
64 am186?cc communications controller data sheet figure 19. software halt cycle waveforms table 13. software halt cycle timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 3t chsv status active delay 0 20 0 12 0 10 ns 4t clsh status inactive delay 020012010ns 5t clav ad address invalid delay 020012010ns 9t chlh ale active delay 201210ns 10 t lhll ale width t clcl C 10 = 30 t clcl C 5 = 20 t clcl C 5 = 15 ns 11 t chll ale inactive delay 20 12 10 ns 19 t dxdl den inactive to dt/r low 2 C1 C1 C1 ns 22 t chctv control active delay 2 3 020012010ns 68 t chav clkout high to a address invalid 020012010ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. testing is performed with equal loading on referenced pins. 3. this parameter applies to the den /ds signal. t4 t1 t2 ti ti 10 19 68 5 9 11 22 3 4 invalid address invalid address clkout a19 Ca0 s6, ad15Cad0 ale den , ds dt/r s2 Cs0
am186?cc communications controller data sheet 65 figure 20. peripheral timing waveforms table 14. peripheral timing 1, 2 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 53 t invch peripheral setup time 10 5 5 ns 54 t cltmv timer output delay 25 15 12 ns 55 t chq0sv queue status 0 output delay 25 15 12 ns 56 t chq1sv queue status 1 output delay 25 15 12 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. pio outputs change anywhere from the beginning of t3 to the first half of t4 of the bus cycle in which the pio data register is written. 53 54 55 clkout int8Cint0, nmi, tmrinx drq0, drq1 tmrout qs0 qs1 56
66 am186?cc communications controller data sheet figure 21. reset waveforms table 15. reset timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 57 t resin res setup time 10 5 5 ns 61 t clro reset delay 18 15 12 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 61 res clkout resout notes: 1. res must be held low for 1 ms during power-up to ensure proper device initialization. 2. diagram is shown for the system pll in its 2x mode of operation. 3. diagram assumes that v cc is stable (i.e., 3.3 v 0.3 v) during the 1-ms res active time. 57
am186?cc communications controller data sheet 67 figure 22. signals related to reset (system pll in 1x or 2x mode) figure 23. signals related to reset (system pll in 4x mode) res clkout resout ad15Cad0 1 all other outputs all pinstrap pins 1, 2 notes: 1. the pinstraps and ad bus are sampled during the assertion of resout for system configuration purposes. 2. for a list of all the pinstraps, refer to table 31, reset configuration pins (pinstraps), on page a-10. res clkout resout ad15Cad0 1 all other outputs all pinstrap pins 1, 2 notes: 1. the pinstraps and ad bus are sampled during the assertion of resout for system configuration purposes. 2. for a list of all the pinstraps, refer to table 31, reset configuration pins (pinstraps), on page a-10.
68 am186?cc communications controller data sheet figure 24. synchronous ready waveforms table 16. external ready cycle timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max ready timing requirements 47 t srycl srdy transition setup time 2 10 5 5 ns 48 t clsry srdy transition hold time 2 32 2 ns 49 t arych ardy resolution transition setup time 3 10 5 5 ns 50 t clarx ardy active hold time 2 43 3 ns 51 t arychl ardy inactive holding time 10 5 5 ns 52 t arylcl ardy setup time 2 15 5 5 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. this timing must be met to guarantee proper operation. 3. this timing must be met to guarantee recognition at the clock edge. t1 t2 t3 tw t4 47 48 tw t3 t2 tw tw t3 tw tw tw t4 t4 t4 clkout srdy case 1 1 case 2 1 case 3 1 case 4 2 case 5 1 t1 t2 t3 t4 notes: 1. normally not ready system. 2. normally ready system. note 1 note 2
am186?cc communications controller data sheet 69 figure 25. asynchronous ready waveforms table 17. bus hold timing 1 notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 5t clav ad address valid delay 0 20 0 12 0 10 ns 15 t claz ad address float delay 0 20 0 12 0 10 ns 18 t chcsx mcsx /pcsx inactive delay 0 20 0 12 0 10 ns 58 t hvcl hold setup 2 2. this timing must be met to guarantee recognition at the next clock. 10 5 5 ns 62 t clhav hlda valid delay 0 20 0 12 0 10 ns 63 t chcz command lines float delay 20 12 10 ns 64 t chcv command lines valid delay (after float) 25 12 10 ns 49 51 50 50 clkout ardy 1 ardy 2 49 (normally not-ready system) (normally ready system) 52 notes: 1. in a normally not ready system, wait states are added after t3 until t arych and t clarx are met. 2. in a normally ready system, a wait state is added if t arych and t arychl during t2 or t arylcl and t clarx during t3 are met. t1 tw t3 t2 t1 case 1 1 case 2 1 case 3 1 case 4 2 case 5 1 t2 t3 tw t4 tw tw t3 tw tw tw t4 t4 t4 t2 t3 t4
70 am186?cc communications controller data sheet figure 26. entering bus hold waveforms figure 27. exiting bus hold waveforms t4 ti ti 58 62 15 63 ti ti ti clkout hold hlda ad15Cad0, den case 1 case 2 a19Ca0, s6, rd , wr , bhe , dt/r , s2 Cs0 , whb , wlb , ucs , lcs , ale mcs3 Cmcs0 , pcs7 Cpcs0 18 ti ti t4 t1 58 62 5 64 ti ti ti t1 clkout hold hlda ad15Cad0, den mcs 3 Cmcs0 ), case 1 case 2 a19Ca0, s6, rd , wr , bhe , dt/r , s2Cs0, whb , wlb , ucs , lcs , ale p cs 7 Cpcs0 )
am186?cc communications controller data sheet 71 table 18. system clocks timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max clkin requirements for 4x pll mode 36 t ckin x1 period 2 not supported 100 125 80 125 ns 37 t clck x1 low time (1.5 v) 45 35ns 38 t chck x1 high time (1.5 v) 45 35 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) 55ns 40 t cklh x1 rise time (1.0 to 3.5 v) 55ns clkin requirements for 2x pll mode 36 t ckin x1 period 2 80 125 50 125 40 125 ns 37 t clck x1 low time (1.5 v) 35 20 15 ns 38 t chck x1 high time (1.5 v) 35 20 15 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) 555ns 40 t cklh x1 rise time (1.0 to 3.5 v) 555ns clkin requirements for 1x pll mode 36 t ckin x1 period 2 40 60 25 60 not supported ns 37 t clck x1 low time (1.5 v) 15 7.5 ns 38 t chck x1 high time (1.5 v) 15 7.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) 55 ns 40 t cklh x1 rise time (1.0 to 3.5 v) 55 ns clkout timing 3 42 t clcl clkout period 40 25 20 ns 43 t clch clkout low time (c l = 50 pf) 0.5t clcl C2 =18 0.5t clcl C1.25 =11.25 0.5t clcl C1 = 9 ns 44 t chcl clkout high time (c l = 50 pf) 0.5t clcl C2 =18 0.5t clcl C1.25 =11.25 0.5t clcl C1 = 9 ns 45 t ch1ch2 clkout rise time (1.0 to 3.5 v) 333ns 46 t cl2cl1 clkout fall time (3.5 to 1.0 v) 333ns 69 t cico x1 to clkout skew 10 10 10 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. testing is performed with equal loading on referenced pins. 3. the pll requires a maximum of 1 ms to achieve lock after all other operating conditions (v cc ) are stable, which is normally achieved by holding res active for at least 1 ms.
72 am186?cc communications controller data sheet figure 28. system clock timing waveformsactive mode (pll 1x mode) figure 29. usb clock timing waveforms 36 37 40 42 44 45 69 38 43 46 x2 x1 clkout 39 table 19. usb clocks timing 1 parameter preliminary unit 48 mhz no. symbol description min max clkin requirements for 4x pll mode 1t uckin usbx1 period 80 85 ns 2t uclck usbx1 low time (1.5 v) 35 ns 3t uchck usbx1 high time (1.5 v) 35 ns 4t uckhl usbx1 fall time (3.5 to 1.0 v) 5 ns 5t ucklh usbx1 rise time (1.0 to 3.5 v) 5 ns clkin requirements for 2x pll mode 1t uckin usbx1 period 40 42 ns 2t uclck usbx1 low time (1.5 v) 15 ns 3t uchck usbx1 high time (1.5 v) 15 ns 4t uckhl usbx1 fall time (3.5 to 1.0 v) 5 ns 5t ucklh usbx1 rise time (1.0 to 3.5 v) 5 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 1 2 3 usbx2 usbx1 4 5
am186?cc communications controller data sheet 73 figure 30. gci bus waveforms table 20. gci bus timing 1 parameter preliminary unit no. symbol description min max 1t wh pulse width high 240 ns 2t wl pulse width low 240 ns 3t sf frame setup 70 ns 4t fh frame hold/clock 20 ns 5t fd frame delay/clock 0 ns 6t wfh frame width high 130 ns 7t dsc data delay/clock 100 2 ns 8t dsf data delay/fsc 100 2 ns 9t dhc data hold/clock 70 2 ns 10 t sd data setup t wh + 20 ns 11 t hd data hold 50 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. c l = 150 pf. 2 5 1 7 3 4 6 gci_dcl_a gci_fsc_a gci_dd_a gci_du_a 8 10 11 9
74 am186?cc communications controller data sheet table 21. pcm highway timing (timing slave) 1, 2 parameter preliminary unit no. symbol description min max 1t clkp pcm clock period 200 ns 2t wh pcm clock high 80 ns 3t wl pcm clock low 80 ns 4t hcf hold time from clk low to fsc valid 0 ns 5t dzf delay time to valid txd from clk 1 25 ns 6t dzf delay time to valid txd from fsc 1 25 ns 7t sufc setup time for fsc high to clk low 35 ns 8t dcd delay time from clk high to txd valid 1 25 ns 9t sudc setup time from rxd valid to clk 35 ns 10 t hcd hold time from clk low to rxd invalid 5 ns 11 t dct delay to tsc valid from clk 1 25 ns 12 t dft delay to tsc valid from fsc 1 25 ns 13 t dclt delay from clk low of last bit to tsc invalid 1 25 ns 14 t hfi hold time from clk low to fsc invalid 0 ns 15 t synss time between successive synchronization pulses 16 clk 16 t wsyn fsc width invalid 8 clk 17 t dtw 3 delay from last bit clk low to txd weak drive 1 25 ns 18 t dtz delay from last bit clk (plus 1) high to txd disable 1 25 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. txd becomes valid after the clk rising edge or fsc enable, whichever is later. 3. during the second half of the last bit transmittal, txd is driven weak so that other devices can safely drive during this ti me.
am186?cc communications controller data sheet 75 figure 31. pcm highway waveforms (timing slave) 4 pcm_clk_x pcm_fsc_x pcm_txd_x 7 8 9 pcm_rxd_x pcm_tsc_x 2 3 1 10 11 12 15 16 17 12 3 4n 13 5 14 6 18 n+1 notes: note that the pcm_txd_x outputs three-state. in the signal description and pin list summary tables, pcm_txd_x is listed as o-ls-od (totem pole output/programmable to hold last state of pin/open drain output) because of the following design characteri stic. on the last bit to be transmitted in pcm highway mode, pcm_txd_x will be driven normally during the first 1/2 bit time. during the last 1/2 bit time of the last bit of the transmission, pcm_txd_x control will be in the hold-last-state condition (ls). in this condition, the output is driven, but at a much weaker strength. this permits another device (external to the microcontroller) t o start driving during this time without bus contention problems. after this 1/2 bit time of hold-last-state condition, the pcm_t xd_x pin will be fully three-stated. in some applications, several pcm highway devices may have their pcm_txd pins tied together. the time slot assigners should be programmed so that only one device is active at any time. the pcm_tsc_x signal permits external bus drivers, possibly to go external to the board. each pcm_tsc_x signal is open- drain so that multiple pcm_tsc_x pins can be connected together. for example, two AM186CC microcontrollers could be con- nected on the same pcm highway and (with proper configuration of the time slot assigners) could occupy different time slots. an external bus driver would need to be active for both AM186CC time slots. the open drain on the pcm_tsc_x pins permits them to be wired together to achieve this.
76 am186?cc communications controller data sheet figure 32. pcm highway waveforms (timing master) table 22. pcm highway timing (timing master) 1 parameter preliminary unit no. symbol description min max 1t dcfh delay time from clk high to fsc high 0 30 ns 2t dcfl delay time from clk high to fsc low 0 30 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. pcm_clk_x pcm_fsc_x 1 2
am186?cc communications controller data sheet 77 figure 33. dce transmit waveforms figure 34. dce receive waveforms table 23. dce interface timing 1, 2 parameter preliminary unit no. symbol description min max 1t tclkper dce clock period 95 ns 2t tclkh dce clock high 40 ns 3t tclkl dce clock low 40 ns 4t tclko dce clock to output delay 1 20 ns 5t tclksu dce clock setup 15 ns 6t tclkhd dce clock hold 5 ns 7t tclkr dce clock rise/fall 10 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. timings are shown with tclk and rclk in the default mode without the optional clock inversion. dce_cts_x 3 1 2 4 4 5 dce_tclk_x dce_txd_x 7 7 6 1 2 3 5 5 4 4 dce_rclk_x dce_rxd_x dce_rtr_x 7 7 6
78 am186?cc communications controller data sheet figure 35. usb data signal rise and fall times figure 36. usb receiver jitter tolerance table 24. usb timing 1, 2 parameter preliminary unit 48 mhz no. symbol description min max 1t r rise time (cl = 50 pf) 4 20 ns 2t f fall time (cl = 50 pf) 4 20 ns 3t jr1 consecutive transition jitter (measured at crossover point) C18.5 18.5 ns 4t jr2 paired transition jitter (measured at crossover point) C9 9 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 2. parameters 3 (t jr1 ) and 4 (t jr2 ) show jitter for the receiver, not the transmitter. see the usb version 1.0 specification for more details. rise time fall time 10% 90% 10% differential data lines (d+/d C) 1 2 clk d+/d C consecutive transition paired transition 3 4
am186?cc communications controller data sheet 79 figure 37. synchronous serial interface waveforms table 25. ssi timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 1t clev clkout low to sden valid 0 20 0 12 0 10 ns 2t clsl clkout low to sclk low 0 20 0 15 0 12 ns 3t dvsh data valid to sclk high 10 5 5 ns 4t shdx sclk high to data invalid 3 2 2 ns 5t sldv sclk low to data valid 20 12 10 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. 1 2 2 3 4 5 clkout sden sclk sdata (rx) sdata (tx) notes: 1. sden is configured to be active high. 2. sclk is configured to be clkout/2. 3. waveforms are shown for normal clock mode (i.e., transmit on negative edge of sclk and receive on positive edge of sclk).
80 am186?cc communications controller data sheet figure 38. dram read cycle without wait-states waveform table 26. dram timing 1 parameter preliminary unit 25 mhz 40 mhz 50 mhz (commercial only) no. symbol description min max min max min max 1t dvcl data in setup 10 5 5 ns 2t cldx data in hold 3 2 2 ns 5t clav ad address valid delay 0 20 0 12 0 10 ns 7t cldv data valid delay 0 20 0 12 0 10 ns 15 t claz ad address float delay 0 20 0 12 0 10 ns 20 t cvctv control active delay 1 0 20 0 12 0 10 ns 25 t clrl rd active delay 0 20 0 12 0 10 ns 27 t clrh rd inactive delay 0 20 0 12 0 10 ns 30 t cldox data hold time 0 0 0 ns 31 t cvctx control inactive delay 0 20 0 12 0 10 ns 68 t chav clkout high to a address valid 0 20 0 12 0 10 ns 402 t colv column address valid delay 0 20 0 12 0 10 ns 403 t chras change in ras delay 3 20 3 12 3 10 ns 404 t chcas change in cas delay 3 20 3 12 3 10 ns notes: 1. all timing parameters are measured at v cc /2 with 50-pf loading on clkout unless otherwise noted. all output test conditions are with the load values shown in table 35, pin list summary, on page a-12. t4 t1 t2 t3 t4 1 2 5 15 68 402 403 403 404 404 25 27 data row addr. clkout ad15 Ca0 a17, a15, a13, a11, ras0 , ras1 cas0 , cas1 rd column a9, a7, a5, a3, a1
am186?cc communications controller data sheet 81 figure 39. dram read cycle with wait-states waveform figure 40. dram write cycle without wait-states waveform t4 t1 t2 tw t3 t4 1 2 5 15 68 402 403 403 404 404 25 27 data row addr. clkout ad15 Cad0 a17, a15, a13, a11, ras0 , ras1 cas0 , ras1 rd column a9, a7, a5, a3, a1 t4 t1 t2 t3 t4 5 7 30 68 402 403 403 404 404 20 31 row addr. clkout ad15 Cad0 ras0 , ras1 cas0 , cas1 wr column data a17, a15, a13, a11, a9, a7, a5, a3, a1
82 am186?cc communications controller data sheet figure 41. dram write cycle with wait-states waveform figure 42. dram refresh cycle waveform 30 t4 t1 t2 tw t3 t4 5 7 68 402 403 403 404 404 20 31 data row addr. clkout ad15 Cad0 a17, a15, a13, a11, ras0 , ras1 cas0 , cas1 wr column a9, a7, a5, a3, a1 t4 t1 t2 tw1 tw2 tw3 t3 t4 5 15 68 402 403 403 404 404 25 27 addr. clkout ad15 Cad0 a17, a15, a13, a11, ras0 , ras1 cas0 , cas1 rd 403 403 column (invalid) row (invalid) a9, a7, a5, a3, a1
am186?cc communications controller data sheet a-1 appendix apin tables this appendix contains pin tables for the AM186CC controller. several different tables are included with the following characteristics: n power-on reset pin defaults including pin numbers and multiplexed functionstable 27 on page a-2. n multiplexed signal trade-offstable 28 on page a-5. n programmable i/o pins ordered by pio pin number and multiplexed signal name, respectively, including pin numbers, multiplexed functions, and pin config- urations following system resettable 29 on page a-8 and table 30 on page a-9. n pinstraps and pinstrap optionstable 31 on page a-10. n pin and signal summary showing signal name and alternate function, pin number, i/o type, maximum load values, power-on reset default function, reset state, por default operation, hold state, and volt- age columntable 35 on page a-12. for pin tables showing pins sorted by pin number and signal name, respectively, see table 1, pqfp pin assignmentssorted by pin number on page 10 and table 2, pqfp pin assignmentssorted by signal name on page 11. for signal descriptions, see table 4, signal descriptions on page 14. in all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). the line over a pin name indicates an active low. the word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it.
a-2 am186?cc communications controller data sheet table 27. power-on reset (por) pin defaults por default pin number multiplexed signal multiplexed signal multiplexed signal pio pinstrap bus interface unit a0 30 a1 31 a2 32 a3 36 a4 37 a5 42 a6 43 a7 44 a8 45 a9 49 a10 50 a11 64 a12 65 a13 69 a14 70 a15 84 a16 85 a17 88 a18 89 a19 90 ad0 28 ad1 34 ad2 38 ad3 46 ad4 51 ad5 66 ad6 86 ad7 92 ad8 29 ad9 35 ad1039 ad1147 ad1252 ad1367 ad1487 ad1593 ale 19 pio33 ardy 14 pio8 bhe 20 pio34 {aden } bsize8 94 den 18 ds pio30 drq1105 dt/r 17 pio29 hlda98 hold99 rd 97 s0 57 {usbxcvr } s1 56 s2 55
am186?cc communications controller data sheet a-3 s6 54 srdy 15 pio35 whb 95 wlb 96 wr 16 pio15 chip selects lcs 131 ras0 mcs1 127 cas1 mcs2 128 cas0 pcs0 5 pio13 {usbsel1} pcs1 6 pio14 {usbsel2} pcs2 7 pcs3 8 ucs 132 {once } reset/clocks clkout60 res 114 resout58 usbx1 75 usbx2 76 x1 73 x2 74 interrupts int0 107 int1 109 int2 110 int3 111 int4 112 int5 113 nmi 115 synchronous communications interfaces channel a (dce) dce_rxd_a 118 gci_dd_a pcm_rxd_a dce_txd_a 119 gci_du_a pcm_txd_a dce_rclk_a 117 gci_dcl_a pcm_clk_a dce_tclk_a 116 gci_fsc_a pcm_fsc_a high-speed uart/hdlc channel d handshaking txd_hu26 debug support qs0 62 qs1 63 universal serial bus usbd+ 81 udpls usbd- 80 udmns pios pio0 144 tmrin1 pio1 143 tmrout1 pio2 10 pcs5 pio3 9 pcs4 {clksel2} pio4 126 mcs0 {ucsx8 } table 27. power-on reset (por) pin defaults (continued) por default pin number multiplexed signal multiplexed signal multiplexed signal pio pinstrap
a-4 am186?cc communications controller data sheet pio5 129 mcs3 ras1 pio6 147 int8 pwd pio7 146 int7 pio9 124 drq0 pio10 2 sden pio11 3 sclk pio12 4 sdata pio16 25 rxd_hu pio17 123 dce_cts_a pcm_tsc_a pio18 122 dce_rtr_a pio19 145 int6 pio20 159 txd_u dce_txd_d pcm_txd_d pio21 22 uclk usbsof usbsci pio22 150 dce_rclk_c pcm_clk_c pio23 149 dce_tclk_c pcm_fsc_c pio24 157 cts_u dce_tclk_d pcm_fsc_d pio25 156 rtr_u dce_rclk_d pcm_clk_d pio26 158 rxd_u dce_rxd_d pcm_rxd_d pio27 142 tmrin0 pio28 141 tmrout0 pio31 13 pcs7 pio32 11 pcs6 pio36 138 dce_rxd_b pcm_rxd_b pio37 139 dce_txd_b pcm_txd_b pio38 137 dce_cts_b pcm_tsc_b pio39 136 dce_rtr_b pio40 135 dce_rclk_b pcm_clk_b pio41 134 dce_tclk_b pcm_fsc_b pio42 153 dce_rxd_c pcm_rxd_c pio43 154 dce_txd_c pcm_txd_c pio44 152 dce_cts_c pcm_tsc_c pio45 151 dce_rtr_c pio46 24 cts_hu dce_cts_d pcm_tsc_d pio47 23 rtr_hu dce_rtr_d reserved 1 rsvd_104 104 uxvrcv rsvd_103 103 uxvoe rsvd_102 102 utxdmns rsvd_101 101 utxdpls notes: 1. for de fault operation and reset states, refer to table 35, pin list summary, on page a-12. table 27. power-on reset (por) pin defaults (continued) por default pin number multiplexed signal multiplexed signal multiplexed signal pio pinstrap
am186?cc communications controller data sheet a-5 table 28. multiplexed signal trade-offs desired function lost function interface name pin interface name interface name interface name interface name memory sram lcs 131 dram ras0 mcs1 127 cas1 mcs2 128 cas0 mcs3 129 ras1 dram cas0 128 sram mcs2 cas1 127 mcs1 ras0 131 lcs ras1 129 mcs3 synchronous communications interfaces dce channel a dce_rxd_a 118 pcm channel a pcm_rxd_a gci channel a gci_dd_a pio dce_txd_a 119 pcm_txd_a gci_du_a dce_rclk_a 117 pcm_clk_a gci_dcl_a dce_tclk_a 116 pcm_fsc_a gci_fsc_a dce_cts_a 123 pcm_tsc_a pio17 dce_rtr_a 122 pio18 dce channel b dce_rxd_b 138 pcm channel b pcm_rxd_b pio pio36 dce_txd_b 139 pcm_txd_b pio37 dce_rclk_b 135 pcm_clk_b pio40 dce_tclk_b 134 pcm_fsc_b pio41 dce_cts_b 137 pcm_tsc_b pio38 dce_rtr_b 136 pio39 dce channel c dce_rxd_c 153 pcm channel c pcm_rxd_c gci to pcm con- version pio pio42 dce_txd_c 154 pcm_txd_c pio43 dce_rclk_c 150 pcm_clk_c pcm_clk_c pio22 dce_tclk_c 149 pcm_fsc_c pcm_fsc_c pio23 dce_cts_c 152 pcm_tsc_c pio44 dce_rtr_c 151 pio45 dce channel d dce_rxd_d 158 pcm channel d pcm_rxd_d low- speed uart rxd_u high- speed uart (flow control) pio pio26 dce_txd_d 159 pcm_txd_d txd_u pio20 dce_rclk_d 156 pcm_clk_d rtr_u pio25 dce_tclk_d 157 pcm_fsc_d cts_u pio24 dce_cts_d 24 pcm_tsc_d cts_hu pio46 dce_rtr_d 23 rtr_hu pio47 pcm channel a pcm_rxd_a 118 dce channel a dce_rxd_a gci channel a gci_dd_a pio pcm_txd_a 119 dce_txd_a gci_du_a pcm_clk_a 117 dce_rclk_a gci_dcl_a pcm_fsc_a 116 dce_tclk_a gci_fsc_a pcm_tsc_a 123 dce_cts_a pio17 pcm channel b pcm_rxd_b 138 dce channel b dce_rxd_b pio pio36 pcm_txd_b 139 dce_txd_b pio37 pcm_clk_b 135 dce_rclk_b pio40 pcm_fsc_b 134 dce_tclk_b pio41 pcm_tsc_b 137 dce_cts_b pio38
a-6 am186?cc communications controller data sheet pcm channel c pcm_rxd_c 153 dce channel c dce_rxd_c gci to pcm con- version pio pio42 pcm_txd_c 154 dce_txd_c pio43 pcm_clk_c 150 dce_rclk_c pcm_clk_c pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 pcm_tsc_c 152 dce_cts_c pio44 pcm channel d pcm_rxd_d 158 dce channel d dce_rxd_d low- speed uart rxd_u high- speed uart pio pio26 pcm_txd_d 159 dce_txd_d txd_u pio20 pcm_clk_d 156 dce_rclk_d rtr_u pio25 pcm_fsc_d 157 dce_tclk_d cts_u pio24 pcm_tsc_d 24 dce_cts_d cts_hu pio46 low- speed uart rxd_u 158 dce channel d dce_rxd_d pcm channel d pcm_rxd_d pio pio26 txd_u 159 dce_txd_d pcm_txd_d pio20 rtr_u 156 dce_rclk_d pcm_clk_d pio25 cts_u 157 dce_tclk_d pcm_fsc_d pio24 high- speed uart rxd_hu 25 dce channel d pcm channel d pio pio16 txd_hu 26 rtr_hu 23 dce_rtr_d pio47 cts_hu 24 dce_cts_d pcm_tsc_d pio46 gci channel a gci_dd_a 118 dce channel a dce_rxd_a pcm channel a pcm_rxd_a pio gci_du_a 119 dce_txd_a pcm_txd_a gci_dcl_a 117 dce_rclk_a pcm_clk_a gci_fsc_a 116 dce_tclk_a pcm_fsc_a gci to pcm con- version pcm_clk_c 150 dce channel c dce_rclk_c pcm channel c pcm_clk_c pio pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 miscellaneous bus interface den 18 bus interface ds ds 18 den clocks uclk 22 clocks usbsof clocks usbsci pio pio21 usbsof 22 uclk usbsci pio21 usbsci 22 uclk usbsof pio21 pios pio0 144 tmrin1 pio1 143 tmrout1 pio2 10 pcs5 pio3 9 pcs4 pio4 126 mcs0 pio5 129 mcs3 ras1 pio6 147 int8 pwd pio7 146 int7 pio8 14 ardy pio9 124 drq0 pio10 2 sden pio11 3 sclk pio12 4 sdata table 28. multiplexed signal trade-offs (continued) desired function lost function interface name pin interface name interface name interface name interface name
am186?cc communications controller data sheet a-7 pio13 5 pcs0 pio14 6 pcs1 pio15 16 wr pio16 25 rxd_hu pio17 123 dce_cts_a pcm_tsc_a pio18 122 dce_rtr_a pio19 145 int6 pio20 159 txd_u dce_txd_d pcm_txd_d pio21 22 uclk usbsof usbsci pio22 150 dce_rclk_c pcm_clk_c pio23 149 dce_tclk_c pcm_fsc_c pio24 157 cts_u dce_tclk_d pcm_fsc_d pio25 156 rtr_u dce_rclk_d pcm_clk_d pio26 158 rxd_u dce_rxd_d pcm_rxd_d pio27 142 tmrin0 pio28 141 tmrout0 pio29 17 dt/r pio30 18 den ds pio31 13 pcs7 pio32 11 pcs6 pio33 19 ale pio34 20 bhe pio35 15 srdy pio36 138 dce_rxd_b pcm_rxd_b pio37 139 dce_txd_b pcm_txd_b pio38 137 dce_cts_b pcm_tsc_b pio39 136 dce_rtr_b pio40 135 dce_rclk_b pcm_clk_b pio41 134 dce_tclk_b pcm_fsc_b pio42 153 dce_rxd_c pcm_rxd_c pio43 154 dce_txd_c pcm_txd_c pio44 152 dce_cts_c pcm_tsc_c pio45 151 dce_rtr_c pio46 24 cts_hu dce_cts_d pcm_tsc_d pio47 23 rtr_hu dce_rtr_d table 28. multiplexed signal trade-offs (continued) desired function lost function interface name pin interface name interface name interface name interface name
a-8 am186?cc communications controller data sheet table 29. pios sorted by pio number pio no. pin no. multiplexed signal multiplexed signal multiplexed signal pin configuration following system reset 1 pio0 144 tmrin1 input with pullup pio1 143 tmrout1 input with pulldown pio2 10 pcs5 input with pullup pio3 9 pcs4 input with pullup pio4 126 mcs0 input with pullup pio5 129 mcs3 ras1 input with pullup pio6 147 int8 pwd input with pullup pio7 146 int7 input with pullup pio8 14 ardy alternate operation 2 pio9 124 drq0 input with pulldown pio10 2 sden input with pulldown pio11 3 sclk input with pullup pio12 4 sdata input with pullup pio13 5 pcs0 alternate operation 2 pio14 6 pcs1 alternate operation 2 pio15 16 wr alternate operation 2 pio16 25 rxd_hu input with pullup pio17 123 dce_cts_a pcm_tsc_a input with pullup pio18 122 dce_rtr_a input with pullup pio19 145 int6 input with pullup pio20 159 txd_u dce_txd_d pcm_txd_d input with pullup pio21 22 uclk usbsof usbsci input with pullup pio22 150 dce_rclk_c pcm_clk_c input with pulldown pio23 149 dce_tclk_c pcm_fsc_c input with pulldown pio24 157 cts_u dce_tclk_d pcm_fsc_d input with pullup pio25 156 rtr_u dce_rclk_d pcm_clk_d input with pullup pio26 158 rxd_u dce_rxd_d pcm_rxd_d input with pullup pio27 142 tmrin0 input with pullup pio28 141 tmrout0 input with pulldown pio29 17 dt/r alternate operation 2 pio30 18 den ds alternate operation 2 pio31 13 pcs7 input with pullup pio32 11 pcs6 input with pullup pio33 19 ale alternate operation 3 pio34 20 bhe alternate operation 2 pio35 15 srdy alternate operation 2 pio36 138 dce_rxd_b pcm_rxd_b input with pullup pio37 139 dce_txd_b pcm_txd_b input with pullup pio38 137 dce_cts_b pcm_tsc_b input with pullup pio39 136 dce_rtr_b input with pullup pio40 135 dce_rclk_b pcm_clk_b input with pullup pio41 134 dce_tclk_b pcm_fsc_b input with pullup pio42 153 dce_rxd_c pcm_rxd_c input with pulldown pio43 154 dce_txd_c pcm_txd_c input with pulldown pio44 152 dce_cts_c pcm_tsc_c input with pullup pio45 151 dce_rtr_c input with pullup pio46 24 cts_hu dce_cts_d pcm_tsc_d input with pullup pio47 23 rtr_hu dce_rtr_d input with pullup notes: 1. system reset is defined as a power-on reset (i.e., the res input pin transitioning from its low to high state) or a reset due to a watchdog timer timeout. 2. when used as a pio, input with pullup option available. 3. when used as a pio, input with a pulldown option available.
am186?cc communications controller data sheet a-9 table 30. pios sorted by signal name signal pio no. pin no. multiplexed signal multiplexed signal pin configuration following system reset 1 ale pio33 19 alternate operation 2 ardy pio8 14 alternate operation 3 bhe pio34 20 alternate operation 3 cts_hu pio46 24 dce_cts_d pcm_tsc_d input with pullup cts_u pio24 157 dce_tclk_d pcm_fsc_d input with pullup dce_cts_a pio17 123 pcm_tsc_a input with pullup dce_cts_b pio38 137 pcm_tsc_b input with pullup dce_cts_c pio44 152 pcm_tsc_c input with pullup dce_rclk_b pio40 135 pcm_clk_b input with pullup dce_rclk_c pio22 150 pcm_clk_c input with pulldown dce_rtr_a pio18 122 input with pullup dce_rtr_b pio39 136 input with pullup dce_rtr_c pio45 151 input with pullup dce_rxd_b pio36 138 pcm_rxd_b input with pullup dce_rxd_c pio42 153 pcm_rxd_c input with pulldown dce_tclk_b pio41 134 pcm_fsc_b input with pullup dce_tclk_c pio23 149 pcm_fsc_c input with pulldown dce_txd_b pio37 139 pcm_txd_b input with pullup dce_txd_c pio43 154 pcm_txd_c input with pulldown den pio30 18 ds alternate operation 3 drq0 pio9 124 input with pulldown dt/r pio29 17 alternate operation 3 int6 pio19 145 input with pullup int7 pio7 146 input with pullup int8 pio6 147 pwd input with pullup mcs0 pio4 126 input with pullup mcs3 pio5 129 ras1 input with pullup pcs0 pio13 5 alternate operation 3 pcs1 pio14 6 alternate operation 3 pcs4 pio3 9 input with pullup pcs5 pio2 10 input with pullup pcs6 pio32 11 input with pullup pcs7 pio31 13 input with pullup rtr_hu pio47 23 dce_rtr_d input with pullup rtr_u pio25 156 dce_rclk_d pcm_clk_d input with pullup rxd_hu pio16 25 input with pullup rxd_u pio26 158 dce_rxd_d pcm_rxd_d input with pullup sclk pio11 3 input with pullup sdata pio12 4 input with pullup sden pio10 2 input with pulldown srdy pio35 15 alternate operation 3 tmrin0 pio27 142 input with pullup tmrin1 pio0 144 input with pullup tmrout0 pio28 141 input with pulldown tmrout1 pio1 143 input with pulldown txd_u pio20 159 dce_txd_d pcm_txd_d input with pullup uclk pio21 22 usbsof usbsci input with pullup wr pio15 16 alternate operation 3 notes: 1. system reset is defined as a power-on reset (i.e., the res input pin transitioning from its low to high state) or a reset due to a watchdog timer timeout. 2. when used as a pio, input with a pulldown option available. 3. when used as a pio, input with a pullup option available.
a-10 am186?cc communications controller data sheet table 31. reset configuration pins (pinstraps) 1 signal name multiplexed signal(s) description {aden }bhe pio34 address enable : if {aden } is held high or left floating during power-on reset, the address portion of the ad bus (ad15Cad0) is enabled or disabled during lcs , ucs , or other memory bus cycles based on how the software configures the da bit setting . in this case, the memory address is accessed on the a19Ca0 pins. there is a weak internal pullup resistor on {aden } so no external pullup is required. this mode of operation reduces power consumption. if {aden } is held low on power-on reset, the ad bus drives both addresses and data, regardless of how software configures the da bit setting. {clksel1} {clksel2} hlda [pcs4 ] pio3 cpu pll mode select 1 determines the pll mode for the system clock source. cpu pll mode select 2 is sampled on the rising edge of reset and determines the pll mode for the system clock source. this pin has an internal pullup resistor that is active only during reset. there are four cpu pll modes that are selected by the values of {clksel1} and {clksel2} as shown in table 32. (for details on clocks see clock generation and control on page 40.) {once } ucs once mode request asserted low places the AM186CC microcontroller into once mode. otherwise, the controller operates normally. in once mode, all pins are three- stated and remain in that state until a subsequent reset occurs. to guarantee that the controller does not inadvertently enter once mode, {once } has a weak internal pullup resistor that is active only during a reset. a reset ending once mode should be as long as a power-on reset for the pll to stabilize. {ucsx8 }[mcs0 ] pio4 upper memory chip select, 8-bit bus asserted low configures the upper chip select region for an 8-bit bus size. this pin has a pullup resistor that is active only during reset, so no external pullup is required to set the bus to 16-bit mode. {usbsel2} {usbsel1} pcs1 pio14 pcs0 pio13 usb clock mode selects 1C2 select the usb pll operating mode. the pins have internal pullups that are active only during reset. the usb pll can operate in one of three modes. with a crystal and the internal usb oscillator or an external oscillator, the usb pll can output 4x or 2x the input frequency. the usb pll can also be disabled and the usb peripheral controller can receive its clock from the cpu pll, which is the default mode. the pins are encoded as shown in table 33. (for details on clocks see clock generation and control on page 40.) {usbxcvr }s0 usb external transceiver enable asserted low disables the internal usb transceiver and enables the pins needed to hook up an external transceiver. this pin has a pullup resistor that is active only during reset, so no external pullup is required as long as the user ensures that this input is not driven low during a power-on reset. notes: 1. a pinstrap is used to enable or disable features based on the state of the pin during an external reset. the pinstrap must b e held in its desired state for at least 4.5 clock cycles after the deassertion of res . the pinstraps are sampled in an external reset only (when res is asserted), not during an internal watchdog timer-generated reset. table 32. cpu pll modes {clksel1} {clksel2} cpu pll mode 1 1 2x, cpu pll enabled (default) 1 0 4x, cpu pll enabled 0 1 1x, cpu pll enabled 0 0 pll bypass table 33. usb pll modes {usbsel1} {usbsel2} usb pll mode 1 1 use system clock (after cpu pll mode select), usb pll disabled (default) 1 0 4x, usb pll enabled 0 1 2x, usb pll enabled 00reserved
am186?cc communications controller data sheet a-11 pin list table column definitions the following paragraphs describes the individual columns of information in table 35, pin list summary, on page a-12. the pins are grouped alphabetically by function. note: all maximum delay numbers should be in- creased by 0.035 ns for every pf of load (up to a max- imum of 150 pf) over the maximum load specified in table 35 on page a-12. column #1signal name, [alternate function], {pinstrap} this column denotes the primary and alternate functions of the pins. most of the pins that have alternate functions are configured for these functions via firmware modifying values in the peripheral control block. refer to the am186?cc/ch/cu microcontrollers register set manual , order #21916, for full documentation of this process. brackets, [ ], are used to indicate the alternate, multiplexed function of a pin (i.e., not power-on reset default). braces, { }, are used to indicate the functionality of a pin only during a processor reset. these signals are called pinstraps. to select the desired configuration, the pinstraps are terminated internally with pullup resistors or externally with pulldown resistors. their state is sampled during a processor reset and latched on the rising edge of reset. the signals must be held in the desired state for 4.5 system clock cycles after the deassertion of reset. based on the pinstraps state at the time they are latched, certain features of the AM186CC controller are enabled or disabled. all external termination should be implemented with 10- kohm resistors on these signals. the pinstraps are listed in table 31, reset configuration pins (pinstraps), on page a-10. column #2pin no. the pin number column identifies the pin number of the individual i/o signal on the package. column #3type definitions of the abbreviations in the type column are shown in table 34. column #4max load (pf) the max load column designates the capacitive load at which the i/o timing for that pin is guaranteed. column #5por default function the por default function column shows the status of these pins after a power-on reset. in some cases the pin is the function outlined in the signal name column of the table. the signal name is listed in the por default function column if the signal is the default function and not a pio after a processor reset. in other cases the pin is a pio configured as an input. column #6reset state the reset state column indicates the termination present on the signal at reset (pullup or pulldown) and indicates whether the signal is a three-stated output or a schmitt trigger input. refer to table 34 for abbreviations used in this column. column #7por default operation the por default operation column describes the type of input and/or output that is default pin operation. refer to table 34 for abbreviations used in this column. column #8hold state the hold state column shows the state of the pin in hold state. refer to table 34 for abbreviations used in this column. column #95 v a "5 v" in the 5-v column indicates 5-v tolerant inputs. these inputs are not damaged and do not draw excess power when driven with levels up to v cc + 2.6 volts. these pins only drive to v cc . table 34. pin list table definitions type definition [ ] pin alternate function { } pinstrap pin b bidirectional hhigh ls programmable to hold last state of pin o totem pole output od open drain output od-o open drain output or totem pole output pd internal pulldown resistor pu internal pullup resistor sti schmitt trigger input sti-od schmitt trigger input or open drain output ts three-state output
a-12 am186?cc communications controller data sheet table 35. pin list summary signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v bus interface unit a0 30 o 70 a0 ts-pd o ts-pd 5 v a1 31 o 70 a1 ts-pd o ts-pd 5 v a2 32 o 70 a2 ts-pd o ts-pd 5 v a3 36 o 70 a3 ts-pd o ts-pd 5 v a4 37 o 70 a4 ts-pd o ts-pd 5 v a5 42 o 70 a5 ts-pd o ts-pd 5 v a6 43 o 70 a6 ts-pd o ts-pd 5 v a7 44 o 70 a7 ts-pd o ts-pd 5 v a8 45 o 70 a8 ts-pd o ts-pd 5 v a9 49 o 70 a9 ts-pd o ts-pd 5 v a10 50 o 70 a10 ts-pd o ts-pd 5 v a11 64 o 70 a11 ts-pd o ts-pd 5 v a12 65 o 70 a12 ts-pd o ts-pd 5 v a13 69 o 70 a13 ts-pd o ts-pd 5 v a14 70 o 70 a14 ts-pd o ts-pd 5 v a15 84 o 70 a15 ts-pd o ts-pd 5 v a16 85 o 70 a16 ts-pd o ts-pd 5 v a17 88 o 70 a17 ts-pd o ts-pd 5 v a18 89 o 70 a18 ts-pd o ts-pd 5 v a19 90 o 70 a19 ts-pd o ts-pd 5 v ad0 28 b 70 ad0 ts-pd b ts 5 v ad1 34 b 70 ad1 ts-pd b ts 5 v ad2 38 b 70 ad2 ts-pd b ts 5 v ad3 46 b 70 ad3 ts-pd b ts 5 v ad4 51 b 70 ad4 ts-pd b ts 5 v ad5 66 b 70 ad5 ts-pd b ts 5 v ad6 86 b 70 ad6 ts-pd b ts 5 v ad7 92 b 70 ad7 ts-pd b ts 5 v ad8 29 b 70 ad8 ts-pd b ts 5 v ad9 35 b 70 ad9 ts-pd b ts 5 v ad10 39 b 70 ad10 ts-pd b ts 5 v ad11 47 b 70 ad11 ts-pd b ts 5 v ad12 52 b 70 ad12 ts-pd b ts 5 v ad13 67 b 70 ad13 ts-pd b ts 5 v ad14 87 b 70 ad14 ts-pd b ts 5 v ad15 93 b 70 ad15 ts-pd b ts 5 v ale [pio33] 19 o sti-pd [sti] [o] 50 ale ts-pd o ts-pd 5 v ardy [pio8] 14 sti-pu sti-pu [sti] [o] 50 ardy sti-pu sti-pu sti 5 v
am186?cc communications controller data sheet a-13 bhe [pio34] {aden } 20 o sti-pu [sti] [o] sti 50 bhe sti-pu o ts-pu 5 v bsize8 94 o 50 bsize8 ts-pu o den [ds ] [pio30] 18 o o sti-pu [sti] [o] 50 den ts-pu o ts-pu 5 v [drq0] pio9 124 sti-pd sti-pd [sti] [o] 50 pio9 sti-pd sti-pd [sti] [o] 5 v drq1 105 sti-pd drq1 sti-pd sti-pd 5 v dt/r [pio29] 17 o sti-pu [sti] [o] 50 dt/r ts-pu o ts-pu 5 v hlda {clksel1} 98 o sti 50 hlda sti-pu o h 5 v hold 99 sti hold sti-pd sti h 5 v rd 97 o 70 rd ts-pu o ts-pu 5 v s0 {usbxcvr } 57 o sti 50 s0 sti-pu o ts 5 v s1 56 o 50 s1 ts-pu o ts 5 v s2 55 o 50 s2 ts-pu o ts 5 v s6 54 o 50 s6 ts-pd o ts 5 v srdy [pio35] 15 sti-pu sti-pu [sti] [o] 50 srdy sti-pu sti-pu 5 v whb 95 o 70 whb ts-pu o ts-pu 5 v wlb 96 o 70 wlb ts-pu o ts-pu 5 v wr [pio15] 16 o sti-pu [sti] [o] sti 50 wr sti-pu o ts-pu 5 v chip selects lcs [ras0 ] 131 o o 50 lcs ts-pu o ts-pu 5 v [mcs0 ] pio4 {ucsx8 } 126 o sti-pu [sti] [o] sti 50 pio4 sti-pu sti-pu [sti] [o] ts-pu 5 v mcs1 [cas1 ] 127 o o 50 mcs1 ts-pu o ts-pu 5 v mcs2 [cas0 ] 128 o o 50 mcs2 ts-pu o ts-pu 5 v [mcs3 ] [ras1 ] pio5 129 o o sti-pu [sti] [o] 50 pio5 sti-pu sti-pu [sti] [o] ts-pu 5 v pcs0 [pio13] {usbsel1} 5 o sti-pu [sti] [o] sti 50 pcs0 sti-pu o ts-pu 5 v pcs1 [pio14] {usbsel2} 6 o sti-pu [sti] [o] sti 50 pcs1 sti-pu o ts-pu 5 v pcs2 7 o 50 pcs2 ts-pu o ts-pu 5 v table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
a-14 am186?cc communications controller data sheet pcs3 8 o 50 pcs3 ts-pu o ts-pu 5 v [pcs4 ] pio3 {clksel2} 9 o sti-pu [sti] [o] sti 50 pio3 sti-pu sti-pu [sti] [o] ts-pu 5 v [pcs5 ] pio2 10 o sti-pu [sti] [o] 50 pio2 sti-pu o ts-pu 5 v [pcs6 ] pio32 11 o sti-pu [sti] [o] 50 pio32 sti-pu sti-pu [sti] [o] ts-pu 5 v [pcs7 ] pio31 13 o sti-pu [sti] [o] 50 pio31 sti-pu sti-pu [sti] [o] ts-pu 5 v ucs {once } 132 o sti 50 ucs sti-pu o ts-pu 5 v reset/clocks clkout 60 o 70 clkout o res 114 st res sti sti 5 v resout 58 o 50 resout h o 5 v [uclk] [usbsof] [usbsci] pio21 22 sti o sti sti-pu [sti] [o] 50 pio21 sti-pu sti-pu [sti] [o] 5 v usbx1 75 sti usbx1 sti usbx2 76 o usbx2 o x1 73 sti x1 sti x2 74 o x2 o programmable timers [tmrin0] pio27 142 sti-pu sti-pu [sti] [o] 50 pio27 sti-pu sti-pu [sti] [o] 5 v [tmrin1] pio0 144 sti-pu sti-pu [sti] [o] 50 pio0 sti-pu sti-pu [sti] [o] 5 v [tmrout0] pio28 141 o sti-pd [sti] [o] 50 pio28 sti-pd sti-pd [sti] [o] ts 5 v [tmrout1] pio1 143 o sti-pd [sti] [o] 50 pio1 sti-pd sti-pd [sti] [o] ts 5 v interrupts int0 107 sti int0 sti-pu sti 5 v int1 109 sti int1 sti-pu sti 5 v int2 110 sti int2 sti-pu sti 5 v int3 111 sti int3 sti-pu sti 5 v int4 112 sti int4 sti-pu sti 5 v int5 113 sti int5 sti-pu sti 5 v [int6] pio19 145 sti sti-pu [sti] [o] 50 pio19 sti-pu sti-pu [sti] [o] 5 v [int7] pio7 146 sti sti-pu [sti] [o] 50 pio7 sti-pu sti-pu [sti] [o] 5 v table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
am186?cc communications controller data sheet a-15 [int8] [pwd] pio6 147 sti sti sti-pu [sti] [o] 50 pio6 sti-pu sti-pu [sti] [o] 5 v nmi 115 sti nmi sti-pu sti 5 v synchronous communications interfaces channel a dce_rxd_a [gci_dd_a] [pcm_rxd_a] 118 sti b-od sti 50 dce_rxd_a sti-pu sti 5 v dce_txd_a [gci_du_a] [pcm_txd_a] 119 o-od b-od o-ls-od 50 dce_txd_a ts-pu od-o 5 v dce_rclk_a [gci_dcl_a] [pcm_clk_a] 117 sti sti sti dce_rclk_a sti-pu sti 5 v dce_tclk_a [gci_fsc_a] [pcm_fsc_a] 116 sti sti sti dce_tclk_a sti-pu sti 5 v [dce_cts_a ] [pcm_tsc_a ] pio17 123 sti od sti-pu [sti] [o] 50 pio17 sti-pu sti-pu [sti] [o] 5 v [dce_rtr_a ] pio18 122 o sti-pu [sti] [o] 30 pio18 sti-pu sti-pu [sti] [o] 5 v channel b [dce_rxd_b] [pcm_rxd_b] pio36 138 sti sti sti-pu [sti] [o] 50 pio36 sti-pu sti-pu [sti] [o] 5 v [dce_txd_b] [pcm_txd_b] pio37 139 od-o o-ls-od sti-pu [sti] [o] 50 pio37 sti-pu sti-pu [sti] [o] 5 v [dce_rclk_b] [pcm_clk_b] pio40 135 sti sti sti-pu [sti] [o] 50 pio40 sti-pu sti-pu [sti] [o] 5 v [dce_tclk_b] [pcm_fsc_b] pio41 134 sti sti sti-pu [sti] [o] 50 pio41 sti-pu sti-pu [sti] [o] 5 v [dce_cts_b ] [pcm_tsc_b ] pio38 137 sti od sti-pu [sti] [o] 50 pio38 sti-pu sti-pu [sti] [o] 5 v [dce_rtr_b ] pio39 136 o sti-pu [sti] [o] 30 pio39 sti-pu sti-pu [sti] [o] 5 v channel c [dce_rxd_c] [pcm_rxd_c] pio42 153 sti sti sti-pd [sti] [o] 50 pio42 sti-pd sti-pd [sti] [o] 5 v [dce_txd_c] [pcm_txd_c] pio43 154 od-o o-ls-od sti-pd [sti] [o] 50 pio43 sti-pd sti-pd [sti] [o] 5 v table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
a-16 am186?cc communications controller data sheet [dce_rclk_c] [pcm_clk_c] pio22 150 sti sti-o sti-pd [sti] [o] 50 pio22 sti-pd sti-pd [sti] [o] 5 v [dce_tclk_c] [pcm_fsc_c] pio23 149 sti sti-o sti-pd [sti] [o] 50 pio23 sti-pd sti-pd [sti] [o] 5 v [dce_cts_c ] [pcm_tsc_c ] pio44 152 sti od sti-pu [sti] [o] 50 pio44 sti-pu sti-pu [sti] [o] 5 v [dce_rtr_c ] pio45 151 o sti-pu [sti] [o] 30 pio45 sti-pu sti-pu [sti] [o] 5 v low-speed uart/synchronous communications channel d [rxd_u] (uart) [dce_rxd_d] [pcm_rxd_d] pio26 158 sti sti sti sti-pu [sti] [o] 50 pio26 sti-pu sti-pu [sti] [o] 5 v [txd_u] (uart) [dce_txd_d] [pcm_txd_d] pio20 159 o od-o o-ls-od sti-pu [sti] [o] 50 pio20 sti-pu sti-pu [sti] [o] 5 v [cts_u ] (uart) [dce_tclk_d] [pcm_fsc_d] pio24 157 sti sti sti sti-pu [sti] [o] 50 pio24 sti-pu sti-pu [sti] [o] 5 v [rtr_u ] (uart) [dce_rclk_d] [pcm_clk_d] pio25 156 o sti sti sti-pu [sti] [o] 30 pio25 sti-pu sti-pu [sti] [o] 5 v high-speed uart [rxd_hu] pio16 25 sti sti-pu [sti] [o] 50 pio16 sti-pu sti-pu [sti] [o] 5 v txd_hu 26 o 30 txd_hu ts-pu o 5 v [cts_hu ] [dce_cts_d ] [pcm_tsc_d ] pio46 24 sti sti od sti-pu [sti] [o] 50 pio46 sti-pu sti-pu [sti] [o] 5 v [rtr_hu ] [dce_rtr_d ] pio47 23 o o sti-pu [sti] [o] 30 pio47 sti-pu sti-pu [sti] [o] 5 v debug support qs0 62 o 30 qs0 ts-pd o 5 v qs1 63 o 30 qs1 ts-pd o 5 v universal serial bus usbd+ [udpls] 81 b sti usbd+ ts b usbd- [udmns] 80 b sti usbd- ts b table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
am186?cc communications controller data sheet a-17 synchronous serial interface [sclk] pio11 3 o sti-pu [sti] [o] 50 pio11 sti-pu sti-pu [sti] [o] 5 v [sdata] pio12 4 o sti-pu [sti] [o] 50 pio12 sti-pu sti-pu [sti] [o] 5 v [sden] pio10 2 o sti-pd [sti] [o] 50 pio10 sti-pd sti-pd [sti] [o] 5 v reserved pins rsvd_104 [uxvrcv] 104 sti sti-pu rsvd_103 [uxvoe ] 103 o 50 ts-pu rsvd_102 [utxdmns] 102 o 50 pu rsvd_101 [utxdpls] 101 o 50 pu power and ground v cc 12 v cc 27 v cc 40 v cc 48 v cc 59 v cc 68 v cc 78 v cc 91 v cc 106 v cc 120 v cc 125 v cc 133 v cc 148 v cc 160 v cc _ a77 v cc _ usb 79 v ss 1 v ss 21 v ss 33 v ss 41 v ss 53 v ss 61 v ss 71 v ss 83 v ss 100 v ss 108 v ss 121 table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
a-18 am186?cc communications controller data sheet v ss 130 v ss 140 v ss 155 v ss _ a72 v ss _ usb 82 table 35. pin list summary (continued) signal name [alternate function] {pinstrap} pin no. type max load (pf) por default function reset state por default operation hold state 5 v
am186?cc communications controller data sheet b-1 appendix bphysical dimensions: pqr160, plastic quad flat pack (pqfp) 25.35 ref 27.90 28.10 31.00 31.40 pin 120 pin 80 0.65 basic 3.20 3.60 0.25 min pin 40 pin 1 i.d. 25.35 ref pin 160 27.90 28.10 31.00 31.40 3.95 max seating plane 16-038-pqr-1 pqr160 12-22-95 lv
b-2 am186?cc communications controller data sheet
am186?cc communications controller data sheet c-1 appendix ccustomer support related amd productse86 ? family devices device description 80c186/80c188 16-bit microcontroller 80l186/80l188 low-voltage, 16-bit microcontroller am186?em/am188?em high-performance, 16-bit embedded microcontroller am186emlv/am188emlv high-performance, 16-bit embedded microcontroller am186es/am188es high-performance, 16-bit embedded microcontroller am186eslv/am188eslv high-performance, 16-bit embedded microcontroller am186ed high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186edlv high-performance, 80c186- and 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186er/am188er high-performance, low-voltage, 16-bit embedded microcontroller with 32 kbyte of in- ternal ram AM186CC high-performance, 16-bit embedded communications controller am186ch high-performance, 16-bit embedded hdlc microcontroller am186cu high-performance, 16-bit embedded usb microcontroller lan?sc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at microcontroller lansc400 single-chip, low-power, pc/at-compatible microcontroller lansc410 single-chip, pc/at-compatible microcontroller lansc520 high-performance, 32-bit embedded microcontroller am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am5 x 86? high-performance, 32-bit embedded microprocessor with 32-bit external data bus amd-k6?e high-performance, 32-bit embedded microprocessor with 64-bit external data bus amd-k6?-2e high-performance, 32-bit embedded microprocessor with 64-bit external data bus and 3dnow!? technology notes: 1. 186 = 16-bit microcontroller and 80c186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit external data bus and 80c188-compatible (except where noted otherwise); lv = low voltage am386 ? sx/dx microprocessors am486 ? dx microprocessor e86 ? family of embedded microprocessors and microcontrollers am186es and am188?em am188emlv microcontrollers am188er microprocessors 16- and 32-bit microcontrollers 16-bit microcontrollers amd-k6?e microprocessor amd-k6?-2e microprocessor am5 x 86? microprocessor AM186CC communications controller am186?cu usb microcontroller am186ch hdlc microcontroller 80c186 and 80c188 microcontrollers am188es microcontrollers am186em and microcontrollers 80l186 and 80l188 microcontrollers am186emlv & microcontrollers am186eslv & am188eslv am186er and microcontrollers am186ed am186edlv microcontroller microcontroller lan?sc310 microcontroller lansc300 microcontroller lansc410 microcontroller lansc400 microcontroller lansc520 microcontroller
c-2 am186?cc communications controller data sheet related documents the following documents provide additional information regarding the AM186CC microcontroller . n am186?cc/ch/cu microcontrollers users manual , order #21914 n am186?cc/ch/cu microcontrollers register set manual , order #21916 n am186? and am188? family instruction set manual , order #21267 n interfacing an am186?cc communications controller to an amd slac? device using the enhanced ssi application note , order #21921 other information of interest includes: n e86? family products and development tools cd, order #21058 AM186CC/ch/cu microcontroller customer development platform the AM186CC/ch/cu customer development platform (cdp) is provided as a test and development platform for the AM186CC/ch/cu microcontrollers. the AM186CC/ch/cu cdp ships with the AM186CC microcontroller. because this device supports a superset of the features of the am186ch hdlc and the am186cu usb microcontrollers, the development platform can be used to evaluate the am186ch and the am186cu devices. the cdp is divided into two major sections: a main board and a development module. the main board serves as the primary platform for silicon evaluation and software development. the board provides connectors for accessing the major communications peripherals, switches to easily configure the microcontroller, logic analyzer, and debug headers. the development module, which attaches to the top of the main board, provides ready-to-run hardware for three of the most common communications requirements: n a 10 mbit/s ethernet connection n an isdn connection (with both an s/t and a u interface) n two pots interfaces the cdp provides a good starting point for hardware designers, and software development can begin immediately without the normal delay that occurs while waiting for prototypes. the cdp also comes with amds codekit software that provides customers with pre-written driver software for the major communications peripherals associated with a typical am186cx design. included are drivers for the hdlc channels, usb peripheral controller (for the am186cu usb microcontroller), uarts, pcnet-isa ii (amds single-chip ethernet solution), and several other common peripherals. the codekit software comes complete with instructions, royalty-free distribution rights, and software in both binary and source code formats. third-party development support products the fusione86 program of partnerships for application solutions provides the customer with an array of products designed to meet critical time-to- market needs. products and solutions available from the amd fusione86 partners include protocol stacks, emulators, hardware and software debuggers, board- level products, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86 and comm86 family hardware and software development questions. note: the support telephone numbers listed below are subject to change. for current telephone numbers, refer to www.amd.com/support/literature . hotline and world wide web support for answers to technical questions, amd provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. the amd world wide web home page provides the latest product information, including technical information and data on upcoming product releases. in addition, epd codekit software on the web site provides tested source code example applications. additional contact information is listed on the back of this datasheet. for technical support questions on all e86 and comm86 products, send e-mail to epd.support@amd.com . corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline
am186?cc communications controller data sheet c-3 world wide web home page to access the amd home page go to: www.amd.com . then follow the embedded processors link for information about e86 and comm86 products. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com . documentation and literature free information such as data books, users manuals, data sheets, application notes, the e86? family products and development tools cd , order #21058, and other literature is available with a simple phone call. internationally, contact your local amd sales office for product literature. additional contact information is listed on the back of this data sheet. literature ordering (800) 222-9323 toll-free for u.s. and canada
c-4 am186?cc communications controller data sheet
am186?cc communications controller data sheet index-1 index a a19Ca0 signals, 14 absolute maximum ratings, 45 ad15Cad0 signals, 14 address and data bus, 14, 17 address bus address bus disable in effect, 36 default operation, 35 description, 14, 17 ale signal, 14 AM186CC controller architectural overview, 28 block diagram, 28 dc characteristics over commercial and industrial operating ranges, 46 detailed description, 28 distinctive characteristics, 1 general description, 1 i/o circuitry, 44 logic diagram by default pin function, 7 logic diagram by interface, 6 ordering information, 2 pin assignment tables, 10 pin tables (appendix a), a-1 pqfp package, b-1 related amd e86 family devices, c-1 signal description table, 14 static operation, 43 applications, 37 32-channel linecard system, 39 isdn terminal adapter system, 38 isdn to ethernet low-end router system, 38 architectural overview, 28 ardy signal, 14 asynchronous communications asynchronous ready waveforms, 69 asynchronous serial ports (description), 31 baud clock, 43 high-speed uart clocks, 43 high-speed uart signal descriptions, 23 uart signal descriptions, 22 b bhe signal, 15 block diagram, 28 bsize8 signal, 15 bus address bus description, 14, 17 bus hold timing, 69 bus status pins, 17 entering bus hold waveforms, 70 exiting bus hold waveforms, 70 bus interface signal list, 14 c capacitance, 46 chip selects description, 34 ranges and dram configuration, 14, 20 signal descriptions, 19 clkout signal, 17 clock clkout signal description, 17 clock generation and control, 40 clock sharing by system and usb, 41 crystal parameters, 42 crystal selection, 42 crystal-driven clock source, 42 external clock source, 43 external interface to support clocks, 42C43 features, 40 high-speed uart clocks, 43 pll bypass mode, 43 suggested system clock frequencies, clock modes and crystal frequencies, 42 system and usb clock generation, 41 system clock, 40 system interfaces and clock control, 33 uart baud clock, 43 usb clock, 40 usb clock timing waveforms, 72 usb clocks timing, 72 cpu am186 embedded cpu, 29 cpu pll modes, a-10
index-2 am186?cc communications controller data sheet crystal crystal-driven clock source, 42 parameters, 42 selecting a crystal, 42 suggested crystal frequencies, 42 customer support documentation and literature, c-3 hotline and web, c-2 literature ordering, c-3 ordering the AM186CC controller, 2 third-party development support products, c-2 web home page, c-3 d dc characteristics over commercial and industrial operating ranges, 46 usb, 46 dce (data communications equipment) dce interface timing, 77 dce receive waveforms, 77 dce transmit waveforms, 77 signal descriptions, 23 dce_rclk_a signal, 23 dce_rclk_d signal, 25 dce_rxd_a signal, 23 dce_rxd_d signal, 24 dce_tclk_a signal, 24 dce_txd_a signal, 23 debug debug support signals, 19 den signal, 15 dma (direct memory access) dma request signals, 15 general-purpose dma channels, 32 smartdma channels, 31 documentation, c-3 dram chip selects and dram configuration, 14 description, 34 read cycle with wait-states waveform, 81 read cycle without wait-states waveform, 80 refresh cycle waveform, 82 signal descriptions, 20 timing, 80 write cycle with wait-states waveform, 82 write cycle without wait-states waveform, 81 driver characteristics - universal serial bus, 45 drq1 signal, 15 dt/r signal, 15 e emulation in-circuit emulator support, 37 evaluation platform, c-2 g gci (general circuit interface) bus timing, 73 bus waveforms, 73 description, 31 signal descriptions, 26 h hdlc (high-level data link control) channels, 31 signal descriptions, 23 high-speed uart signal descriptions, 23 hlda signal, 16 hold signal, 16 hotline and world wide web support, c-2 i i/o i/o circuitry, 44 i/o space, 29 programmable i/o (pio), 32 int5Cint0 signals, 21 interrupts interrupt controller, 32 signal descriptions, 21 l lcs signal, 19 logic diagram by default pin function, 7 logic diagram by interface, 6 m mcs1 signal, 19 mcs2 signal, 19 memory memory organization, 29 segment register selection rules, 30 memory and peripheral interface, 33 multiplexed functions signal trade-offs, a-5
am186?cc communications controller data sheet index-3 n nmi signal, 21 o operating ranges, 45 ordering information, 2 p package pqfp physical dimensions, b-1 pcm (pulse-code modulation) highway signal descriptions, 25 timing (timing master), 76 timing (timing slave), 74 waveforms (timing master), 76 waveforms (timing slave), 75 pcs0 signal, 20 pcs1 signal, 20 pcs2 signal, 20 pcs3 signal, 20 peripherals memory and peripheral interface, 33 peripheral timing, 65 peripheral timing waveforms, 65 system interfaces, 32 pins pin and signal tables, 9 pin assignments sorted by pin number, 10 pin assignments sorted by signal name, 11 pin connection diagram, 8 pin defaults, a-2 pin list summary, a-12 pin tables (appendix a), a-1 pinstraps pinstraps table, a-10 pio supply current limit, 44 pio47Cpio0 signals, 22 pios (programmable i/os) description, 32 signal descriptions, 22 sorted by pin number, a-8 sorted by signal name, a-9 pll (phase-locked loop) modes, a-10 pll bypass (cpu), a-10 pll bypass mode, 43 system pll, 40 usb pll, 40 pll bypass mode, 43 por (power-on reset) pin defaults, a-2 power power consumption calculation, 47 power supply operation, 44 supply connections, 44 supply current, 47 typical icc versus frequency, 47 pqfp package physical dimensions, b-1 q qs1Cqs0 signal, 19 r rd signal, 16 read cycle timing, 58 read cycle waveforms, 60 res signal, 18 reset definition of types, 13 power-on reset pin defaults table, a-2 signals related to reset, 67 timing, 66 waveforms, 66 reset configuration pins see pinstraps, a-10 resout signal, 18 rsvd_101 pin, 18 rsvd_102 pin, 18 rsvd_103 pin, 18 rsvd_104 pin, 18 s s0 signal, 17 s1 signal, 17 s2 signal, 17 s6 signal, 16 serial communications asynchronous serial ports, 31 description, 30 gci, 31 hdlc, 31 smartdma, 31 synchronous serial port, 32 tsas, 31 usb, 30
index-4 am186?cc communications controller data sheet signals multiplexed signal trade-offs table, a-5 pin and signal tables, 9 pin assignments sorted by signal name, 11 signal descriptions, 14 signals related to reset, 67 smartdma channels, 31 software halt cycle timing, 64 software halt cycle waveforms, 64 srdy signal, 16 static operation, 43 switching characteristics and waveforms key to switching waveforms, 49 numerical key to switching parameter symbols, 54 over commercial/industrial operating ranges, 58 parameter symbols, 50 synchronous serial interface (ssi) signal descriptions, 23 synchronous ready waveforms, 68 synchronous serial port, 32 timing, 79 waveforms, 79 system system clock timing waveforms, 72 system clocks timing, 71 t thermal characteristics, 48 equations, 48 thermal resistance, 48 timers programmable timers, 32 signal descriptions, 22 timing asynchronous ready waveforms, 69 bus hold, 69 dce interface, 77 dram, 80 external ready cycle, 68 gci, 73 pcm highway, 74C76 peripheral timing, 65 read cycle timing, 58 reset, 66 software halt cycle, 64 ssi, 79 synchronous ready waveforms, 68 system clocks, 71 usb, 78 usb clocks, 72 write cycle timing, 61 tsas (time slot assigners) description, 31 txd_hu signal, 23 u uart, 23 asynchronous ready waveforms, 69 asynchronous serial ports (description), 31 baud clock, 43 high-speed uart clocks, 43 high-speed uart signal descriptions, 23 uart signal descriptions, 22 ucs signal, 20 universal serial bus driver characteristics, 45 usb clock, 40 clock timing waveforms, 72 clocks timing, 72 data signal rise and fall times, 78 description, 30 external transceiver signals, 26 pll modes, a-10 receiver jitter tolerance, 78 signal descriptions, 26 system and usb clock generation, 41 timing, 78 usbdC signal, 26 usbd+ signal, 26 usbx1 signal, 18 usbx2 signal, 18 utxdmns signal, 27 utxdpls signal, 27 uxvoe signal, 27 uxvrcv signal, 27 w watchdog timer description, 33 res and watchdog timer reset, 18 whb signal, 17 wlb signal, 17 wr signal, 17 write cycle timing, 61 write cycle waveforms, 63 www home page, c-3 support, c-2
am186?cc communications controller data sheet index-5 x x1 signal, 18 x2 signal, 18
am186?cc communications controller data sheet trademarks 2000 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am5 x 86, am386, and am486 are registered trademarks, and amd-k6, 3dnow!, am186, am188, codekit, comm86, e86, lan, pcnet, slac, and smartdma are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repr esentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. ? 2000 advanced micro devices, inc. all rights reserved.

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